Lines Matching defs:tex
1341 /* For normal tex instructions */
1424 sam->cat5.tex = info.tex_idx;
2728 get_tex_dest_type(nir_tex_instr *tex)
2732 switch (tex->dest_type) {
2756 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2759 glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2762 /* note: would use tex->coord_components.. except txs.. also,
2769 if (tex->is_shadow && tex->op != nir_texop_lod)
2772 if (tex->is_array && tex->op != nir_texop_lod)
2781 * version of the tex instruction which encode tex/samp as immediates:
2784 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2788 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2789 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2796 if (tex->texture_non_uniform || tex->sampler_non_uniform)
2806 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2823 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2868 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2874 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2882 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2883 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2885 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2894 MAX2(ctx->max_texture_index, tex->texture_index);
2895 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2896 info.tex_idx = tex->texture_index;
2900 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2903 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2904 info.samp_idx = tex->texture_index;
2914 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2927 ncomp = nir_dest_num_components(tex->dest);
2932 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2934 for (unsigned i = 0; i < tex->num_srcs; i++) {
2935 switch (tex->src[i].src_type) {
2937 coord = ir3_get_src(ctx, &tex->src[i].src);
2940 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2944 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2948 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2951 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2955 off = ir3_get_src(ctx, &tex->src[i].src);
2959 ddx = ir3_get_src(ctx, &tex->src[i].src);
2962 ddy = ir3_get_src(ctx, &tex->src[i].src);
2965 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2974 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2975 tex->src[i].src_type);
2980 switch (tex->op) {
2991 ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2993 ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
3020 switch (tex->component) {
3040 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
3044 tex_info(tex, &flags, &coords);
3057 /* insert tex coords: */
3084 if (tex->is_shadow && tex->op != nir_texop_lod)
3087 if (tex->is_array && tex->op != nir_texop_lod)
3096 if (tex->op == nir_texop_txd) {
3119 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
3139 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
3152 type = get_tex_dest_type(tex);
3157 if (tex->op == nir_texop_txf_ms_fb) {
3170 info = get_tex_samp_tex_src(ctx, tex);
3174 if (tex->op == nir_texop_tg4 && ctx->compiler->gen == 4 &&
3175 ctx->sampler_swizzles[tex->texture_index] != 0x688 /* rgba */) {
3176 uint16_t swizzles = ctx->sampler_swizzles[tex->texture_index];
3177 uint16_t swizzle = (swizzles >> (tex->component * 3)) & 7;
3186 ir3_put_dst(ctx, &tex->dest);
3197 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
3199 compile_assert(ctx, tex->src[idx].src.is_ssa);
3203 sam->prefetch.input_offset = ir3_nir_coord_offset(tex->src[idx].src.ssa);
3206 sam->prefetch.tex = info.tex_idx;
3221 uint8_t tex_bits = ctx->sampler_swizzles[tex->texture_index] >> 12;
3255 } else if ((ctx->astc_srgb & (1 << tex->texture_index)) &&
3256 tex->op != nir_texop_tg4 && /* leave out tg4, unless it's on alpha? */
3257 !nir_tex_instr_is_query(tex)) {
3281 bool half = nir_dest_bit_size(tex->dest) == 16;
3293 ir3_put_dst(ctx, &tex->dest);
3297 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
3301 type_t dst_type = get_tex_dest_type(tex);
3302 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
3304 dst = ir3_get_dst(ctx, &tex->dest, 1);
3319 ir3_put_dst(ctx, &tex->dest);
3323 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
3329 type_t dst_type = get_tex_dest_type(tex);
3330 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
3332 tex_info(tex, &flags, &coords);
3338 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
3341 dst = ir3_get_dst(ctx, &tex->dest, 4);
3343 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
3346 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
3348 if (tex->sampler_dim != GLSL_SAMPLER_DIM_BUF) {
3366 if (tex->is_array) {
3374 ir3_put_dst(ctx, &tex->dest);
3504 nir_tex_instr *tex = nir_instr_as_tex(instr);
3505 /* couple tex instructions get special-cased:
3507 switch (tex->op) {
3509 emit_tex_txs(ctx, tex);
3512 emit_tex_info(ctx, tex, 2);
3515 emit_tex_info(ctx, tex, 3);
3518 emit_tex(ctx, tex);
4419 /* Fixup tex sampler state for astc/srgb workaround instructions. We
4420 * need to assign the tex state indexes for these after we know the
4421 * max tex index.
4427 /* indexed by original tex idx, value is newly assigned alpha sampler
4428 * state tex idx. Zero is invalid since there is at least one sampler
4440 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
4442 if (alt_tex_state[sam->cat5.tex] == 0) {
4443 /* assign new alternate/alpha tex state slot: */
4444 alt_tex_state[sam->cat5.tex] = tex_idx++;
4445 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
4449 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
4453 /* Fixup tex sampler state for tg4 workaround instructions. We
4454 * need to assign the tex state indexes for these after we know the
4455 * max tex index.
4461 /* indexed by original tex idx, value is newly assigned alpha sampler
4462 * state tex idx. Zero is invalid since there is at least one sampler
4474 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
4476 if (alt_tex_state[sam->cat5.tex] == 0) {
4477 /* assign new alternate/alpha tex state slot: */
4478 alt_tex_state[sam->cat5.tex] = tex_idx++;
4479 so->tg4.orig_idx[idx++] = sam->cat5.tex;
4483 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
4568 fetch->tex_bindless_id = instr->prefetch.tex;
4572 fetch->tex_id = instr->prefetch.tex;