Lines Matching defs:src
128 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
152 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
172 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
192 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
263 return src;
265 struct ir3_instruction *cov = ir3_COV(ctx->block, src, src_type, dst_type);
283 resize_shift_amount(struct ir3_context *ctx, struct ir3_instruction *src,
287 return src;
289 return ir3_COV(ctx->block, src, TYPE_U32, TYPE_U16);
295 struct ir3_instruction **src)
301 accumulator = src[2];
304 dst[0] = ir3_DP4ACC(ctx->block, src[0], 0, src[1], 0, accumulator, 0);
317 dst[0] = ir3_ADD_U(ctx->block, dst[0], 0, src[2], 0);
327 struct ir3_instruction **src)
342 accumulator = src[2];
345 dst[0] = ir3_DP2ACC(ctx->block, src[0], 0, src[1], 0, accumulator, 0);
349 dst[0] = ir3_DP2ACC(ctx->block, src[0], 0, src[1], 0, dst[0], 0);
354 dst[0] = ir3_ADD_U(ctx->block, dst[0], 0, src[2], 0);
357 dst[0] = ir3_ADD_S(ctx->block, dst[0], 0, src[2], 0);
366 struct ir3_instruction **dst, *src[info->num_inputs];
391 nir_alu_src *asrc = &alu->src[i];
396 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
397 if (!src[i])
398 src[i] = create_immed_typed(ctx->block, 0, dst_type);
399 dst[i] = ir3_MOV(b, src[i], dst_type);
410 nir_alu_src *asrc = &alu->src[0];
411 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
425 /* General case: We can just grab the one used channel per src. */
428 nir_alu_src *asrc = &alu->src[i];
433 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
434 bs[i] = nir_src_bit_size(asrc->src);
436 compile_assert(ctx, src[i]);
465 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
469 dst[0] = create_cov(ctx, create_cov(ctx, src[0], 32, nir_op_f2f16_rtne),
474 b, src[0], 0,
484 b, src[0], 0,
497 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
506 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
510 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
513 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
516 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
519 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
522 /* if there is just a single use of the src, and it supports
524 * src instruction and create a mov. This is easier for cp
527 if (alu->src[0].src.is_ssa && is_sat_compatible(src[0]->opc) &&
528 (list_length(&alu->src[0].src.ssa->uses) == 1)) {
529 src[0]->flags |= IR3_INSTR_SAT;
530 dst[0] = ir3_MOV(b, src[0], dst_type);
535 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
540 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
543 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
546 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
549 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
553 dst[0] = ir3_DSX(b, src[0], 0);
557 dst[0] = ir3_DSXPP_MACRO(b, src[0], 0);
562 dst[0] = ir3_DSY(b, src[0], 0);
567 dst[0] = ir3_DSYPP_MACRO(b, src[0], 0);
571 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
575 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
579 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
583 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
587 dst[0] = ir3_CEIL_F(b, src[0], 0);
590 dst[0] = ir3_FLOOR_F(b, src[0], 0);
593 dst[0] = ir3_TRUNC_F(b, src[0], 0);
596 dst[0] = ir3_RNDNE_F(b, src[0], 0);
599 dst[0] = ir3_SIGN_F(b, src[0], 0);
603 dst[0] = ir3_SIN(b, src[0], 0);
606 dst[0] = ir3_COS(b, src[0], 0);
609 dst[0] = ir3_RSQ(b, src[0], 0);
612 dst[0] = ir3_RCP(b, src[0], 0);
615 dst[0] = ir3_LOG2(b, src[0], 0);
618 dst[0] = ir3_EXP2(b, src[0], 0);
621 dst[0] = ir3_SQRT(b, src[0], 0);
625 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
628 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
631 dst[0] = ir3_ADD_S(b, src[0], 0, src[1], 0);
635 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
639 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
642 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
645 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
648 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
651 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
654 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
657 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
660 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
664 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
667 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
670 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
676 dst[0] = ir3_SUB_U(b, one, 0, src[0], 0);
678 dst[0] = ir3_NOT_B(b, src[0], 0);
682 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
686 ir3_SHL_B(b, src[0], 0, resize_shift_amount(ctx, src[1], bs[0]), 0);
690 ir3_ASHR_B(b, src[0], 0, resize_shift_amount(ctx, src[1], bs[0]), 0);
693 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
696 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
700 ir3_SHR_B(b, src[0], 0, resize_shift_amount(ctx, src[1], bs[0]), 0);
703 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
707 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
711 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
715 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
719 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
723 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
728 struct ir3_instruction *cond = src[0];
730 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
748 if (is_half(src[1]) != is_half(cond)) {
750 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
759 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
763 if (is_half(src[1])) {
764 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
766 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
772 if (ctx->compiler->gen < 5 || (src[0]->dsts[0]->flags & IR3_REG_HALF)) {
773 dst[0] = ir3_CBITS_B(b, src[0], 0);
781 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0), TYPE_U32,
783 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
789 // if the src's were half precision, to make this less awkward.. otoh
801 dst[0] = ir3_CLZ_S(b, src[0], 0);
809 dst[0] = ir3_CLZ_B(b, src[0], 0);
811 0, src[0], 0, dst[0], 0);
814 dst[0] = ir3_BFREV_B(b, src[0], 0);
818 dst[0] = ir3_BFREV_B(b, src[0], 0);
822 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
826 dst[0] = ir3_ADD_S(b, src[0], 0, src[1], 0);
830 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
834 dst[0] = ir3_SUB_S(b, src[0], 0, src[1], 0);
843 emit_alu_dot_4x8_as_dp4acc(ctx, alu, dst, src);
845 emit_alu_dot_4x8_as_dp2acc(ctx, alu, dst, src);
894 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
895 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
902 ir3_handle_bindless_cat6(ldc, intr->src[0]);
921 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
922 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
927 ir3_handle_bindless_cat6(ldc, intr->src[0]);
949 /* First src is ubo index, which could either be an immed or not: */
950 src0 = ir3_get_src(ctx, &intr->src[0])[0];
972 if (nir_src_is_const(intr->src[1])) {
973 off += nir_src_as_uint(intr->src[1]);
975 /* For load_ubo_indirect, second src is indirect offset: */
976 src1 = ir3_get_src(ctx, &intr->src[1])[0];
1015 /* Load a kernel param: src[] = { address }. */
1026 struct ir3_instruction *src0 = ir3_get_src(ctx, &intr->src[0])[0];
1050 /* src[] = { block_index } */
1056 struct ir3_instruction *ibo = ir3_ssbo_to_ibo(ctx, intr->src[0]);
1064 ir3_handle_bindless_cat6(resinfo, intr->src[0]);
1077 /* src[] = { offset }. const_index[] = { base } */
1086 offset = ir3_get_src(ctx, &intr->src[0])[0];
1101 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
1110 value = ir3_get_src(ctx, &intr->src[0]);
1111 offset = ir3_get_src(ctx, &intr->src[1])[0];
1122 stl->cat6.type = utype_src(intr->src[0]);
1129 /* src[] = { offset }. const_index[] = { base } */
1139 offset = ir3_get_src(ctx, &intr->src[0])[0];
1158 /* src[] = { value, offset }. const_index[] = { base } */
1167 value = ir3_get_src(ctx, &intr->src[0]);
1168 offset = ir3_get_src(ctx, &intr->src[1])[0];
1180 store->cat6.type = utype_src(intr->src[0]);
1210 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1211 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1245 src1 = ir3_collect(b, ir3_get_src(ctx, &intr->src[2])[0], src1);
1265 stp_ldp_offset(struct ir3_context *ctx, nir_src *src,
1270 if (nir_src_is_const(*src)) {
1271 unsigned src_offset = nir_src_as_uint(*src);
1282 *offset = ir3_get_src(ctx, src)[0];
1286 /* src[] = { offset }. */
1295 stp_ldp_offset(ctx, &intr->src[0], &offset, &base);
1309 /* src[] = { value, offset }. const_index[] = { write_mask } */
1319 value = ir3_get_src(ctx, &intr->src[0]);
1321 stp_ldp_offset(ctx, &intr->src[1], &offset, &base);
1331 stp->cat6.type = utype_src(intr->src[0]);
1350 get_image_ssbo_samp_tex_src(struct ir3_context *ctx, nir_src *src)
1354 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(*src);
1365 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1367 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1388 texture = ir3_get_src(ctx, src)[0];
1394 unsigned slot = nir_src_as_uint(*src);
1429 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1446 !ir3_bindless_resource(intr->src[0]) &&
1447 !nir_src_is_const(intr->src[0])) {
1453 struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0]);
1455 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &intr->src[1]);
1495 struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0]);
1501 assert(nir_src_as_uint(intr->src[1]) == 0);
1531 /* src[] = { buffer_index, offset }. No const_index */
1539 !ir3_bindless_resource(intr->src[0]) ||
1546 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[2])[0];
1548 struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0]);
1871 * sub.s tmp, src, 8
1903 struct ir3_register *src =
1905 src->wrmask = dst->wrmask;
1906 src->def = dst;
1973 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2014 __ssa_src(scan, src, 0);
2040 struct ir3_instruction *const *src;
2058 if (nir_src_is_const(intr->src[0])) {
2059 idx += nir_src_as_uint(intr->src[0]);
2066 src = ir3_get_src(ctx, &intr->src[0]);
2071 ir3_get_addr0(ctx, src[0], 1));
2174 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
2450 src = ir3_get_src(ctx, &intr->src[0]);
2451 cond = src[0];
2493 src = ir3_get_src(ctx, &intr->src[0]);
2494 cond = src[0];
2517 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2518 struct ir3_instruction *pred = ir3_get_predicate(ctx, src);
2540 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2541 struct ir3_instruction *cond = ir3_get_src(ctx, &intr->src[1])[0];
2543 src, 0);
2552 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2553 dst[0] = ir3_READ_FIRST_MACRO(ctx->block, src, 0);
2562 if (nir_src_is_const(intr->src[0]) && nir_src_as_bool(intr->src[0])) {
2566 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2567 struct ir3_instruction *pred = ir3_get_predicate(ctx, src);
2582 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2583 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[1])[0];
2590 dst[0] = ir3_QUAD_SHUFFLE_BRCST(ctx->block, src, 0, idx, 0);
2596 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2597 dst[0] = ir3_QUAD_SHUFFLE_HORIZ(ctx->block, src, 0);
2603 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2604 dst[0] = ir3_QUAD_SHUFFLE_VERT(ctx->block, src, 0);
2610 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2611 dst[0] = ir3_QUAD_SHUFFLE_DIAG(ctx->block, src, 0);
2623 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
2652 unsigned components = nir_src_num_components(intr->src[0]);
2657 struct ir3_instruction *src =
2658 ir3_create_collect(b, ir3_get_src(ctx, &intr->src[0]), components);
2669 ir3_STC(ctx->block, create_immed(b, dst_lo), 0, src, 0);
2806 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2809 tex_const = nir_src_is_const(bindless_tex->src[0]);
2811 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2823 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2826 samp_const = nir_src_is_const(bindless_samp->src[0]);
2828 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2868 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2874 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2885 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2900 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2935 switch (tex->src[i].src_type) {
2937 coord = ir3_get_src(ctx, &tex->src[i].src);
2940 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2944 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2948 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2951 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2955 off = ir3_get_src(ctx, &tex->src[i].src);
2959 ddx = ir3_get_src(ctx, &tex->src[i].src);
2962 ddy = ir3_get_src(ctx, &tex->src[i].src);
2965 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2974 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2975 tex->src[i].src_type);
3199 compile_assert(ctx, tex->src[idx].src.is_ssa);
3203 sam->prefetch.input_offset = ir3_nir_coord_offset(tex->src[idx].src.ssa);
3346 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
3415 struct ir3_instruction *src =
3417 if (src)
3418 __ssa_src(continue_phi, src, 0);
3428 if (nsrc->src.ssa->parent_instr->type == nir_instr_type_ssa_undef) {
3432 return ir3_get_src(ctx, &nsrc->src)[0];
3455 struct ir3_instruction *src = read_phi_src(ctx, pred, phi, nphi);
3456 if (src) {
3457 __ssa_src(phi, src, 0);
3492 /* ignored, handled as part of the intrinsic they are src to */
3917 coord = ir3_create_collect(ctx->block, ir3_get_src(ctx, &intr->src[0]), 2);
3919 compile_assert(ctx, nir_src_is_const(intr->src[coord ? 1 : 0]));
3922 unsigned offset = nir_src_as_uint(intr->src[coord ? 1 : 0]);
3983 /* fixup the src wrmask to avoid validation fail */
4118 compile_assert(ctx, nir_src_is_const(intr->src[1]));
4120 unsigned offset = nir_src_as_uint(intr->src[1]);
4154 slot += io.dual_source_blend_index; /* For dual-src blend */
4226 struct ir3_instruction *const *src = ir3_get_src(ctx, &intr->src[0]);
4229 ctx->outputs[idx] = src[i];
4577 fetch->src = instr->prefetch.input_offset;