Lines Matching defs:outputs
1174 /* for a650, use STL for vertex outputs used by tess ctrl shader: */
3839 out = ctx->outputs[regid(strmout->output[i].register_index, c)];
4199 compile_assert(ctx, so->outputs_count <= ARRAY_SIZE(so->outputs));
4201 so->outputs[n].slot = slot;
4203 so->outputs[n].view = offset;
4208 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
4221 if (!ctx->outputs[idx]) {
4222 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
4229 ctx->outputs[idx] = src[i];
4301 ctx->outputs =
4513 /* first pass, remove unused outputs from the IR level outputs: */
4516 unsigned slot = so->outputs[outidx].slot;
4526 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
4530 unsigned slot = so->outputs[i].slot;
4533 so->outputs[j] = so->outputs[i];
4635 * NOP and has an epilogue that writes the VS outputs to local storage, to
4645 struct ir3_instruction *outputs[3];
4652 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
4655 outputs[outputs_count] = out;
4666 so->outputs[n].slot = VARYING_SLOT_REL_PATCH_ID_IR3;
4668 outputs[outputs_count] = out;
4676 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
4678 outputs[outputs_count] = out;
4686 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
4688 outputs[outputs_count] = out;
4700 __ssa_src(chmask, outputs[i], 0)->num = regids[i];
4713 struct ir3_instruction *outputs[ctx->noutputs / 4];
4724 /* Setup IR level outputs, which are "collects" that gather
4725 * the scalar components of outputs.
4735 if (!ctx->outputs[i + j])
4749 ir3_create_collect(b, &ctx->outputs[i], ncomp);
4755 outputs[outputs_count] = out;
4789 __ssa_src(end, outputs[i], 0);
4797 /* at this point, for binning pass, throw away unneeded outputs: */
4820 /* at this point, for binning pass, throw away unneeded outputs:
4827 /* cleanup the result of removing unneeded outputs: */
4910 * Fixup inputs/outputs to point to the actual registers assigned:
4913 * 2) iterate IR level inputs/outputs and update the variants
4914 * inputs/outputs table based on the assigned registers for
4915 * the remaining inputs/outputs.
4921 so->outputs[i].regid = INVALID_REG;
4929 so->outputs[outidx].regid = reg->num;
4930 so->outputs[outidx].half = !!(reg->flags & IR3_REG_HALF);