Lines Matching defs:end
2143 struct ir3_instruction *end = ir3_PREDE(b);
2144 array_insert(b, b->keeps, end);
2146 end->barrier_class = IR3_BARRIER_EVERYTHING;
2147 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
3378 * their srcs until the end of the shader, since (eg. loops) one of
3675 * that control reconverges at the end of each loop iteration.
3737 * (nir) end block, and nir ensures that all flow control paths terminate
3738 * into the end block. We re-purpose the original end block to generate
3740 * block holding stream-out write instructions, followed by the new end
3772 /* at this point, we are at the original 'end' block,
3774 * append stream-out block and new-end block
3882 * into which we emit the 'end' instruction.
3888 * which the 'end' instruction lands).
4211 /* if varying packing doesn't happen, we could end up in a situation
4504 unreachable("couldn't find end instruction");
4508 fixup_binning_pass(struct ir3_context *ctx, struct ir3_instruction *end)
4514 for (i = 0, j = 0; i < end->srcs_count; i++) {
4515 unsigned outidx = end->end.outidxs[i];
4519 end->srcs[j] = end->srcs[i];
4520 end->end.outidxs[j] = end->end.outidxs[i];
4524 end->srcs_count = j;
4536 for (unsigned k = 0; k < end->srcs_count; k++) {
4537 if (end->end.outidxs[k] == i) {
4538 end->end.outidxs[k] = j;
4702 chmask->end.outidxs = ralloc_array(chmask, unsigned, outputs_count);
4703 memcpy(chmask->end.outidxs, outidxs, sizeof(unsigned) * outputs_count);
4717 /* Insert these collect's in the block before the end-block if
4785 struct ir3_instruction *end =
4789 __ssa_src(end, outputs[i], 0);
4792 end->end.outidxs = ralloc_array(end, unsigned, outputs_count);
4793 memcpy(end->end.outidxs, outidxs, sizeof(unsigned) * outputs_count);
4795 array_insert(ctx->block, ctx->block->keeps, end);
4799 fixup_binning_pass(ctx, end);
4923 struct ir3_instruction *end = find_end(so->ir);
4925 for (unsigned i = 0; i < end->srcs_count; i++) {
4926 unsigned outidx = end->end.outidxs[i];
4927 struct ir3_register *reg = end->srcs[i];