Lines Matching defs:dst
294 struct ir3_instruction **dst,
304 dst[0] = ir3_DP4ACC(ctx->block, src[0], 0, src[1], 0, accumulator, 0);
308 dst[0]->cat3.signedness = IR3_SRC_UNSIGNED;
310 dst[0]->cat3.signedness = IR3_SRC_MIXED;
317 dst[0] = ir3_ADD_U(ctx->block, dst[0], 0, src[2], 0);
318 dst[0]->flags |= IR3_INSTR_SAT;
320 dst[0]->flags |= IR3_INSTR_SAT;
326 struct ir3_instruction **dst,
345 dst[0] = ir3_DP2ACC(ctx->block, src[0], 0, src[1], 0, accumulator, 0);
346 dst[0]->cat3.packed = IR3_SRC_PACKED_LOW;
347 dst[0]->cat3.signedness = signedness;
349 dst[0] = ir3_DP2ACC(ctx->block, src[0], 0, src[1], 0, dst[0], 0);
350 dst[0]->cat3.packed = IR3_SRC_PACKED_HIGH;
351 dst[0]->cat3.signedness = signedness;
354 dst[0] = ir3_ADD_U(ctx->block, dst[0], 0, src[2], 0);
355 dst[0]->flags |= IR3_INSTR_SAT;
357 dst[0] = ir3_ADD_S(ctx->block, dst[0], 0, src[2], 0);
358 dst[0]->flags |= IR3_INSTR_SAT;
366 struct ir3_instruction **dst, *src[info->num_inputs];
380 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
399 dst[i] = ir3_MOV(b, src[i], dst_type);
415 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
417 dst[i] = NULL;
465 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
469 dst[0] = create_cov(ctx, create_cov(ctx, src[0], 32, nir_op_f2f16_rtne),
473 dst[0] = ir3_CMPS_F(
476 dst[0]->cat2.condition = IR3_COND_NE;
483 dst[0] = ir3_CMPS_S(
486 dst[0]->cat2.condition = IR3_COND_NE;
497 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
506 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
510 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
513 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
516 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
519 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
530 dst[0] = ir3_MOV(b, src[0], dst_type);
535 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
536 dst[0]->flags |= IR3_INSTR_SAT;
540 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
543 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
546 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
549 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
553 dst[0] = ir3_DSX(b, src[0], 0);
554 dst[0]->cat5.type = TYPE_F32;
557 dst[0] = ir3_DSXPP_MACRO(b, src[0], 0);
558 dst[0]->cat5.type = TYPE_F32;
562 dst[0] = ir3_DSY(b, src[0], 0);
563 dst[0]->cat5.type = TYPE_F32;
567 dst[0] = ir3_DSYPP_MACRO(b, src[0], 0);
568 dst[0]->cat5.type = TYPE_F32;
571 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
572 dst[0]->cat2.condition = IR3_COND_LT;
575 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
576 dst[0]->cat2.condition = IR3_COND_GE;
579 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
580 dst[0]->cat2.condition = IR3_COND_EQ;
583 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
584 dst[0]->cat2.condition = IR3_COND_NE;
587 dst[0] = ir3_CEIL_F(b, src[0], 0);
590 dst[0] = ir3_FLOOR_F(b, src[0], 0);
593 dst[0] = ir3_TRUNC_F(b, src[0], 0);
596 dst[0] = ir3_RNDNE_F(b, src[0], 0);
599 dst[0] = ir3_SIGN_F(b, src[0], 0);
603 dst[0] = ir3_SIN(b, src[0], 0);
606 dst[0] = ir3_COS(b, src[0], 0);
609 dst[0] = ir3_RSQ(b, src[0], 0);
612 dst[0] = ir3_RCP(b, src[0], 0);
615 dst[0] = ir3_LOG2(b, src[0], 0);
618 dst[0] = ir3_EXP2(b, src[0], 0);
621 dst[0] = ir3_SQRT(b, src[0], 0);
625 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
628 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
631 dst[0] = ir3_ADD_S(b, src[0], 0, src[1], 0);
632 dst[0]->dsts[0]->flags |= IR3_REG_EI;
635 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
636 dst[0]->dsts[0]->flags |= IR3_REG_EI;
639 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
642 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
645 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
648 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
651 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
654 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
657 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
660 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
664 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
667 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
670 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
676 dst[0] = ir3_SUB_U(b, one, 0, src[0], 0);
678 dst[0] = ir3_NOT_B(b, src[0], 0);
682 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
685 dst[0] =
689 dst[0] =
693 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
696 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
699 dst[0] =
703 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
704 dst[0]->cat2.condition = IR3_COND_LT;
707 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
708 dst[0]->cat2.condition = IR3_COND_GE;
711 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
712 dst[0]->cat2.condition = IR3_COND_EQ;
715 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
716 dst[0]->cat2.condition = IR3_COND_NE;
719 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
720 dst[0]->cat2.condition = IR3_COND_LT;
723 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
724 dst[0]->cat2.condition = IR3_COND_GE;
764 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
766 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
773 dst[0] = ir3_CBITS_B(b, src[0], 0);
788 // TODO maybe the builders should default to making dst half-precision
794 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
795 dst[0]->dsts[0]->flags |= IR3_REG_HALF;
796 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
801 dst[0] = ir3_CLZ_S(b, src[0], 0);
802 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
804 dst[0] = ir3_SEL_B32(b, ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0),
805 0, cmp, 0, dst[0], 0);
809 dst[0] = ir3_CLZ_B(b, src[0], 0);
810 dst[0] = ir3_SEL_B32(b, ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0),
811 0, src[0], 0, dst[0], 0);
814 dst[0] = ir3_BFREV_B(b, src[0], 0);
815 dst[0] = ir3_CLZ_B(b, dst[0], 0);
818 dst[0] = ir3_BFREV_B(b, src[0], 0);
822 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
823 dst[0]->flags |= IR3_INSTR_SAT;
826 dst[0] = ir3_ADD_S(b, src[0], 0, src[1], 0);
827 dst[0]->flags |= IR3_INSTR_SAT;
830 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
831 dst[0]->flags |= IR3_INSTR_SAT;
834 dst[0] = ir3_SUB_S(b, src[0], 0, src[1], 0);
835 dst[0]->flags |= IR3_INSTR_SAT;
843 emit_alu_dot_4x8_as_dp4acc(ctx, alu, dst, src);
845 emit_alu_dot_4x8_as_dp2acc(ctx, alu, dst, src);
884 struct ir3_instruction **dst)
907 ir3_split_dest(b, dst, ldc, 0, ncomp);
939 struct ir3_instruction **dst)
1011 dst[i] = load;
1019 struct ir3_instruction **dst)
1034 dst[0] = create_uniform(b, p + (offset / 4));
1045 dst[0] = create_uniform_indirect(b, offset / 4, TYPE_U32,
1053 struct ir3_instruction **dst)
1068 ir3_split_dest(b, dst, resinfo, 0, 1);
1073 *dst = ir3_ADD_U(b, ir3_SHL_B(b, resinfo_dst[1], 0, create_immed(b, 16), 0), 0, resinfo_dst[0], 0);
1080 struct ir3_instruction **dst)
1098 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
1133 struct ir3_instruction **dst)
1155 ir3_split_dest(b, dst, load, 0, intr->num_components);
1289 struct ir3_instruction **dst)
1306 ir3_split_dest(b, dst, ldp, 0, intr->num_components);
1432 struct ir3_instruction **dst)
1438 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1448 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1485 ir3_split_dest(b, dst, sam, 0, 4);
1492 struct ir3_instruction **dst)
1511 * Note use a temporary dst and then copy, since the size of the dst
1520 dst[i] = tmp[i];
1524 dst[ncoords - 1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1526 dst[ncoords - 1] = ir3_MOV(b, tmp[3], TYPE_U32);
1535 struct ir3_instruction **dst)
1541 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1560 ir3_split_dest(b, dst, sam, 0, num_components);
1825 struct ir3_instruction **dst)
1853 ir3_split_dest(ctx->block, dst, ij, 0, 2);
1873 * mov.u32f32 dst, tmp
1896 create_multidst_mov(struct ir3_block *block, struct ir3_register *dst)
1899 unsigned dst_flags = dst->flags & IR3_REG_HALF;
1900 unsigned src_flags = dst->flags & (IR3_REG_HALF | IR3_REG_SHARED);
1905 src->wrmask = dst->wrmask;
1906 src->def = dst;
1907 assert(!(dst->flags & IR3_REG_RELATIV));
1909 (dst->flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32;
2020 struct ir3_register *dst;
2022 case nir_intrinsic_reduce: dst = reduce; break;
2023 case nir_intrinsic_inclusive_scan: dst = inclusive; break;
2024 case nir_intrinsic_exclusive_scan: dst = exclusive; break;
2029 return create_multidst_mov(ctx->block, dst);
2039 struct ir3_instruction **dst;
2046 dst = ir3_get_dst(ctx, &intr->dest, dest_components);
2048 dst = NULL;
2061 dst[i] = create_uniform_typed(
2068 dst[i] = create_uniform_indirect(
2086 dst[0] = create_uniform(b, primitive_param + 0);
2089 dst[0] = create_uniform(b, primitive_param + 1);
2092 dst[0] = create_uniform(b, primitive_param + 2);
2095 dst[0] = create_uniform(b, primitive_param + 3);
2098 dst[0] = create_uniform(b, primitive_param + 4);
2099 dst[1] = create_uniform(b, primitive_param + 5);
2102 dst[0] = create_uniform(b, primitive_param + 6);
2103 dst[1] = create_uniform(b, primitive_param + 7);
2108 dst[0] = create_uniform(b, primitive_map + idx);
2112 dst[0] = ctx->gs_header;
2115 dst[0] = ctx->tcs_header;
2119 dst[0] = ctx->rel_patch_id;
2127 dst[0] = ctx->primitive_id;
2135 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
2138 dst[2] = create_immed(b, 0);
2154 ctx->funcs->emit_intrinsic_load_global_ir3(ctx, intr, dst);
2158 emit_intrinsic_load_ubo(ctx, intr, dst);
2161 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
2167 ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4);
2178 ir3_split_dest(b, dst, offset, 0, 2);
2187 dst[0] = ctx->ij[IJ_PERSP_CENTER_RHW];
2192 emit_intrinsic_barycentric(ctx, intr, dst);
2199 emit_intrinsic_load_kernel_input(ctx, intr, dst);
2206 emit_intrinsic_load_ssbo(ctx, intr, dst);
2212 emit_intrinsic_ssbo_size(ctx, intr, dst);
2224 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
2227 emit_intrinsic_load_shared(ctx, intr, dst);
2242 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
2245 emit_intrinsic_load_scratch(ctx, intr, dst);
2252 emit_intrinsic_load_image(ctx, intr, dst);
2260 ctx->funcs->emit_intrinsic_image_size(ctx, intr, dst);
2282 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
2304 dst[0] = ctx->basevertex;
2310 dst[0] = ctx->draw_id;
2316 dst[0] = ctx->base_instance;
2323 dst[0] = ctx->view_index;
2333 dst[0] = ctx->vertex_id;
2340 dst[0] = ctx->instance_id;
2350 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
2357 dst[0] = ctx->samp_mask_in;
2363 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
2376 dst[0] = ir3_CMPS_S(b, ctx->frag_face, 0,
2378 dst[0]->cat2.condition = IR3_COND_EQ;
2385 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
2395 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
2399 dst[i] = create_driver_param(ctx, IR3_DP_WORKGROUP_ID_X + i);
2405 dst[i] = create_driver_param(ctx, IR3_DP_BASE_GROUP_X + i);
2410 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
2415 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
2423 dst[0] = create_driver_param(ctx, size);
2427 dst[0] = create_driver_param(ctx, IR3_DP_SUBGROUP_ID_SHIFT);
2430 dst[0] = create_driver_param(ctx, IR3_DP_WORK_DIM);
2434 dst[0] = ir3_GETFIBERID(b);
2435 dst[0]->cat6.type = TYPE_U32;
2436 __ssa_dst(dst[0]);
2520 dst[0] = ir3_ANY_MACRO(ctx->block, pred, 0);
2522 dst[0] = ir3_ALL_MACRO(ctx->block, pred, 0);
2523 dst[0]->srcs[0]->num = regid(REG_P0, 0);
2524 array_insert(ctx->ir, ctx->ir->predicates, dst[0]);
2528 dst[0] = ir3_ELECT_MACRO(ctx->block);
2535 dst[0] = ir3_SHPS_MACRO(ctx->block);
2542 dst[0] = ir3_READ_COND_MACRO(ctx->block, ir3_get_predicate(ctx, cond), 0,
2544 dst[0]->dsts[0]->flags |= IR3_REG_SHARED;
2545 dst[0]->srcs[0]->num = regid(REG_P0, 0);
2546 array_insert(ctx->ir, ctx->ir->predicates, dst[0]);
2553 dst[0] = ir3_READ_FIRST_MACRO(ctx->block, src, 0);
2554 dst[0]->dsts[0]->flags |= IR3_REG_SHARED;
2577 ir3_split_dest(ctx->block, dst, ballot, 0, components);
2590 dst[0] = ir3_QUAD_SHUFFLE_BRCST(ctx->block, src, 0, idx, 0);
2591 dst[0]->cat5.type = dst_type;
2597 dst[0] = ir3_QUAD_SHUFFLE_HORIZ(ctx->block, src, 0);
2598 dst[0]->cat5.type = type_uint_size(nir_dest_bit_size(intr->dest));
2604 dst[0] = ir3_QUAD_SHUFFLE_VERT(ctx->block, src, 0);
2605 dst[0]->cat5.type = type_uint_size(nir_dest_bit_size(intr->dest));
2611 dst[0] = ir3_QUAD_SHUFFLE_DIAG(ctx->block, src, 0);
2612 dst[0]->cat5.type = type_uint_size(nir_dest_bit_size(intr->dest));
2617 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
2623 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
2635 dst[0] = ctx->funcs->emit_intrinsic_atomic_global(ctx, intr);
2642 dst[0] = emit_intrinsic_reduce(ctx, intr);
2653 unsigned dst = nir_intrinsic_base(intr);
2654 unsigned dst_lo = dst & 0xff;
2655 unsigned dst_hi = dst >> 8;
2693 struct ir3_instruction **dst =
2699 dst[i] = create_immed_typed(ctx->block, instr->value[i].u8, TYPE_U8);
2702 dst[i] = create_immed_typed(ctx->block, instr->value[i].u16, TYPE_U16);
2705 dst[i] = create_immed_typed(ctx->block, instr->value[i].u32, TYPE_U32);
2712 struct ir3_instruction **dst =
2720 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
2917 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2932 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
3185 dst[i] = imm;
3219 ir3_split_dest(b, dst, sam, 0, 4);
3245 dst[i] = ir3_MAD_F32(b, dst[i], 0, create_immed(b, fui((1 << bits) - 1)), 0, create_immed(b, fui(0.5f)), 0);
3247 dst[i] = ir3_COV(b, dst[i], TYPE_F32, TYPE_U32);
3250 dst[i] = ir3_SHL_B(b, dst[i], 0, create_immed(b, 32 - bits), 0);
3251 dst[i] = ir3_ASHR_B(b, dst[i], 0, create_immed(b, 32 - bits), 0);
3262 ir3_split_dest(b, dst, sam, 0, 3);
3273 ir3_split_dest(b, &dst[3], sam, 3, 1);
3276 ir3_split_dest(b, dst, sam, 0, ncomp);
3287 dst[i] = ir3_MUL_F(
3288 b, ir3_COV(b, dst[i], TYPE_S32, half ? TYPE_F16 : TYPE_F32), 0,
3300 struct ir3_instruction **dst, *sam;
3304 dst = ir3_get_dst(ctx, &tex->dest, 1);
3311 ir3_split_dest(b, dst, sam, idx, 1);
3317 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
3326 struct ir3_instruction **dst, *sam;
3341 dst = ir3_get_dst(ctx, &tex->dest, 4);
3359 ir3_split_dest(b, dst, sam, 0, 4);
3368 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
3370 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
3385 struct ir3_instruction *phi, **dst;
3390 dst = ir3_get_dst(ctx, &nphi->dest, 1);
3397 dst[0] = phi;
4576 fetch->dst = instr->dsts[0]->num;
4582 assert(fetch->dst <= 0x3f);