Lines Matching defs:compiler
67 ir3_compiler_destroy(struct ir3_compiler *compiler)
69 disk_cache_destroy(compiler->disk_cache);
70 ralloc_free(compiler);
155 struct ir3_compiler *compiler = rzalloc(NULL, struct ir3_compiler);
165 compiler->dev = dev;
166 compiler->dev_id = dev_id;
167 compiler->gen = fd_dev_gen(dev_id);
168 compiler->robust_buffer_access2 = options->robust_buffer_access2;
171 compiler->local_mem_size = 32 * 1024;
173 compiler->branchstack_size = 64;
174 compiler->wave_granularity = 2;
175 compiler->max_waves = 16;
177 compiler->max_variable_workgroup_size = 1024;
179 const struct fd_dev_info *dev_info = fd_dev_info(compiler->dev_id);
181 if (compiler->gen >= 6) {
182 compiler->samgq_workaround = true;
199 compiler->max_const_pipeline = 512;
200 compiler->max_const_frag = 512;
201 compiler->max_const_geom = 512;
202 compiler->max_const_safe = 100;
209 compiler->max_const_compute = 256;
212 compiler->has_clip_cull = true;
215 compiler->has_pvtmem = true;
217 compiler->has_preamble = true;
219 compiler->tess_use_shared = dev_info->a6xx.tess_use_shared;
221 compiler->storage_16bit = dev_info->a6xx.storage_16bit;
223 compiler->has_getfiberid = dev_info->a6xx.has_getfiberid;
225 compiler->has_dp2acc = dev_info->a6xx.has_dp2acc;
226 compiler->has_dp4acc = dev_info->a6xx.has_dp4acc;
228 compiler->shared_consts_base_offset = 504;
229 compiler->shared_consts_size = 8;
230 compiler->geom_shared_consts_size_quirk = 16;
232 compiler->max_const_pipeline = 512;
233 compiler->max_const_geom = 512;
234 compiler->max_const_frag = 512;
235 compiler->max_const_compute = 512;
240 compiler->max_const_safe = 256;
243 if (compiler->gen >= 6) {
244 compiler->reg_size_vec4 = dev_info->a6xx.reg_size_vec4;
245 } else if (compiler->gen >= 4) {
249 compiler->reg_size_vec4 = 48;
252 compiler->reg_size_vec4 = 96;
255 if (compiler->gen >= 6) {
256 compiler->threadsize_base = 64;
257 } else if (compiler->gen >= 4) {
261 compiler->threadsize_base = 32;
263 compiler->threadsize_base = 8;
266 if (compiler->gen >= 4) {
268 compiler->flat_bypass = true;
269 compiler->levels_add_one = false;
270 compiler->unminify_coords = false;
271 compiler->txf_ms_with_isaml = false;
272 compiler->array_index_add_half = true;
273 compiler->instr_align = 16;
274 compiler->const_upload_unit = 4;
277 compiler->flat_bypass = false;
278 compiler->levels_add_one = true;
279 compiler->unminify_coords = true;
280 compiler->txf_ms_with_isaml = true;
281 compiler->array_index_add_half = false;
282 compiler->instr_align = 4;
283 compiler->const_upload_unit = 8;
286 compiler->bool_type = (compiler->gen >= 5) ? TYPE_U16 : TYPE_U32;
287 compiler->has_shared_regfile = compiler->gen >= 5;
289 compiler->push_ubo_with_preamble = options->push_ubo_with_preamble;
293 assert(compiler->has_preamble);
295 if (compiler->gen >= 6) {
296 compiler->nir_options = nir_options_a6xx;
297 compiler->nir_options.has_udot_4x8 = dev_info->a6xx.has_dp2acc;
298 compiler->nir_options.has_sudot_4x8 = dev_info->a6xx.has_dp2acc;
300 compiler->nir_options = nir_options;
301 /* a2xx compiler doesn't handle indirect: */
302 if (compiler->gen <= 2)
303 compiler->nir_options.force_indirect_unrolling = nir_var_all;
306 /* 16-bit ALU op generation is mostly controlled by frontend compiler options, but
309 if (compiler->gen >= 5 && !(ir3_shader_debug & IR3_DBG_NOFP16))
310 compiler->nir_options.support_16bit_alu = true;
313 ir3_disk_cache_init(compiler);
315 return compiler;
319 ir3_get_compiler_options(struct ir3_compiler *compiler)
321 return &compiler->nir_options;