Lines Matching defs:instr
37 #include "instr-a3xx.h"
202 struct ir3_instruction *instr;
432 * ie. use the ir3_count_instructions pass, and then use instr->ip
715 struct ir3_instruction *ir3_instr_clone(struct ir3_instruction *instr);
716 void ir3_instr_add_dep(struct ir3_instruction *instr,
718 const char *ir3_instr_name(struct ir3_instruction *instr);
720 struct ir3_register *ir3_src_create(struct ir3_instruction *instr, int num,
722 struct ir3_register *ir3_dst_create(struct ir3_instruction *instr, int num,
735 void ir3_reg_set_last_array(struct ir3_instruction *instr,
739 void ir3_instr_set_address(struct ir3_instruction *instr,
743 ir3_instr_check_mark(struct ir3_instruction *instr)
745 if (instr->flags & IR3_INSTR_MARK)
747 instr->flags |= IR3_INSTR_MARK;
758 * Move 'instr' to just before 'after'
761 ir3_instr_move_before(struct ir3_instruction *instr,
764 list_delinit(&instr->node);
765 list_addtail(&instr->node, &after->node);
769 * Move 'instr' to just after 'before':
772 ir3_instr_move_after(struct ir3_instruction *instr,
775 list_delinit(&instr->node);
776 list_add(&instr->node, &before->node);
780 * Move 'instr' to the beginning of the block:
783 ir3_instr_move_before_block(struct ir3_instruction *instr,
786 list_delinit(&instr->node);
787 list_add(&instr->node, &block->instr_list);
792 void ir3_set_dst_type(struct ir3_instruction *instr, bool half);
793 void ir3_fixup_src_type(struct ir3_instruction *instr);
797 bool ir3_valid_flags(struct ir3_instruction *instr, unsigned n, unsigned flags);
799 bool ir3_valid_immediate(struct ir3_instruction *instr, int32_t immed);
821 is_flow(struct ir3_instruction *instr)
823 return (opc_cat(instr->opc) == 0);
827 is_kill_or_demote(struct ir3_instruction *instr)
829 return instr->opc == OPC_KILL || instr->opc == OPC_DEMOTE;
833 is_nop(struct ir3_instruction *instr)
835 return instr->opc == OPC_NOP;
859 is_same_type_mov(struct ir3_instruction *instr)
863 switch (instr->opc) {
865 if (instr->cat1.src_type != instr->cat1.dst_type)
870 if (!is_same_type_reg(instr->dsts[0], instr->srcs[0]))
875 if (instr->flags & IR3_INSTR_SAT)
880 if (!is_same_type_reg(instr->dsts[0], instr->srcs[0]))
884 return instr->srcs_count == 1;
889 dst = instr->dsts[0];
907 is_const_mov(struct ir3_instruction *instr)
909 if (instr->opc != OPC_MOV)
912 if (!(instr->srcs[0]->flags & IR3_REG_CONST))
915 type_t src_type = instr->cat1.src_type;
916 type_t dst_type = instr->cat1.dst_type;
924 is_subgroup_cond_mov_macro(struct ir3_instruction *instr)
926 switch (instr->opc) {
942 is_alu(struct ir3_instruction *instr)
944 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
948 is_sfu(struct ir3_instruction *instr)
950 return (opc_cat(instr->opc) == 4) || instr->opc == OPC_GETFIBERID;
954 is_tex(struct ir3_instruction *instr)
956 return (opc_cat(instr->opc) == 5);
960 is_tex_or_prefetch(struct ir3_instruction *instr)
962 return is_tex(instr) || (instr->opc == OPC_META_TEX_PREFETCH);
966 is_mem(struct ir3_instruction *instr)
968 return (opc_cat(instr->opc) == 6) && instr->opc != OPC_GETFIBERID;
972 is_barrier(struct ir3_instruction *instr)
974 return (opc_cat(instr->opc) == 7);
978 is_half(struct ir3_instruction *instr)
980 return !!(instr->dsts[0]->flags & IR3_REG_HALF);
984 is_shared(struct ir3_instruction *instr)
986 return !!(instr->dsts[0]->flags & IR3_REG_SHARED);
990 is_store(struct ir3_instruction *instr)
995 switch (instr->opc) {
1012 is_load(struct ir3_instruction *instr)
1014 switch (instr->opc) {
1033 is_input(struct ir3_instruction *instr)
1039 switch (instr->opc) {
1050 is_bool(struct ir3_instruction *instr)
1052 switch (instr->opc) {
1131 is_meta(struct ir3_instruction *instr)
1133 return (opc_cat(instr->opc) == -1);
1158 dest_regs(struct ir3_instruction *instr)
1160 if (instr->dsts_count == 0)
1163 assert(instr->dsts_count == 1);
1164 return util_last_bit(instr->dsts[0]->wrmask);
1179 writes_gpr(struct ir3_instruction *instr)
1181 if (dest_regs(instr) == 0)
1183 return is_dest_gpr(instr->dsts[0]);
1187 writes_addr0(struct ir3_instruction *instr)
1190 if (instr->dsts_count > 0) {
1191 struct ir3_register *dst = instr->dsts[0];
1198 writes_addr1(struct ir3_instruction *instr)
1201 if (instr->dsts_count > 0) {
1202 struct ir3_register *dst = instr->dsts[0];
1209 writes_pred(struct ir3_instruction *instr)
1212 if (instr->dsts_count > 0) {
1213 struct ir3_register *dst = instr->dsts[0];
1246 return reg->def->instr;
1464 ir3_output_conv_type(struct ir3_instruction *instr, bool *can_fold)
1467 switch (instr->opc) {
1525 * into the op. We can assume that instr has folded in a conversion from
1530 ir3_output_conv_src_type(struct ir3_instruction *instr, type_t base_type)
1532 switch (instr->opc) {
1541 return (instr->dsts[0]->flags & IR3_REG_HALF) ? half_type(base_type)
1559 return (instr->srcs[0]->flags & IR3_REG_HALF) ? half_type(base_type)
1565 ir3_output_conv_dst_type(struct ir3_instruction *instr, type_t base_type)
1567 return (instr->dsts[0]->flags & IR3_REG_HALF) ? half_type(base_type)
1625 __ssa_src_cnt(struct ir3_instruction *instr)
1627 return instr->srcs_count + instr->deps_count;
1631 __is_false_dep(struct ir3_instruction *instr, unsigned n)
1633 if (n >= instr->srcs_count)
1639 __ssa_srcp_n(struct ir3_instruction *instr, unsigned n)
1641 if (__is_false_dep(instr, n))
1642 return &instr->deps[n - instr->srcs_count];
1643 if (ssa(instr->srcs[n]))
1644 return &instr->srcs[n]->def->instr;
1657 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1664 /* iterator for an instruction's SSA sources (instr): */
1716 void ir3_print_instr(struct ir3_instruction *instr);
1719 void ir3_print_instr_stream(struct log_stream *stream, struct ir3_instruction *instr);
1728 struct ir3_instruction *instr, bool mergedregs);
1733 is_local_mem_load(struct ir3_instruction *instr)
1735 return instr->opc == OPC_LDL || instr->opc == OPC_LDLV ||
1736 instr->opc == OPC_LDLW;
1741 is_ss_producer(struct ir3_instruction *instr)
1743 foreach_dst (dst, instr) {
1747 return is_sfu(instr) || is_local_mem_load(instr);
1752 soft_ss_delay(struct ir3_instruction *instr)
1764 if (is_sfu(instr) || is_local_mem_load(instr))
1774 is_sy_producer(struct ir3_instruction *instr)
1776 return is_tex_or_prefetch(instr) ||
1777 (is_load(instr) && !is_local_mem_load(instr)) ||
1778 is_atomic(instr->opc);
1782 soft_sy_delay(struct ir3_instruction *instr, struct ir3 *shader)
1790 unsigned components = reg_elems(instr->dsts[0]);
1803 if (instr->opc == OPC_LDC) {
1808 } else if (is_tex_or_prefetch(instr)) {
1883 foreach_instr (instr, &block->instr_list) {
1884 if (is_tex_or_prefetch(instr))
1887 if (is_load(instr)) {
1888 switch (instr->opc) {
1908 __ssa_src(struct ir3_instruction *instr, struct ir3_instruction *src,
1914 reg = ir3_src_create(instr, INVALID_REG, IR3_REG_SSA | flags);
1921 __ssa_dst(struct ir3_instruction *instr)
1923 struct ir3_register *reg = ir3_dst_create(instr, INVALID_REG, IR3_REG_SSA);
1924 reg->instr = instr;
1990 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV, 1, 1);
1993 __ssa_dst(instr)->flags |= flags;
1995 struct ir3_register *src_reg = __ssa_src(instr, src, IR3_REG_ARRAY);
1998 __ssa_src(instr, src, src->dsts[0]->flags & IR3_REG_SHARED);
2001 instr->cat1.src_type = type;
2002 instr->cat1.dst_type = type;
2003 return instr;
2010 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV, 1, 1);
2016 __ssa_dst(instr)->flags |= dst_flags;
2017 __ssa_src(instr, src, 0);
2018 instr->cat1.src_type = src_type;
2019 instr->cat1.dst_type = dst_type;
2021 return instr;
2027 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOVMSK, 1, 0);
2029 struct ir3_register *dst = __ssa_dst(instr);
2032 instr->repeat = components - 1;
2033 return instr;
2040 struct ir3_instruction *instr =
2043 struct ir3_register *dst = __ssa_dst(instr);
2047 __ssa_src(instr, src, 0);
2049 return instr;
2062 struct ir3_instruction *instr = ir3_instr_create(block, opc, 1, 0); \
2063 instr->flags |= flag; \
2064 return instr; \
2075 struct ir3_instruction *instr = \
2078 __ssa_dst(instr); \
2079 __ssa_src(instr, a, aflags); \
2080 instr->flags |= flag; \
2081 return instr; \
2094 struct ir3_instruction *instr = ir3_instr_create(block, opc, dst_count, 2); \
2096 __ssa_dst(instr); \
2097 __ssa_src(instr, a, aflags); \
2098 __ssa_src(instr, b, bflags); \
2099 instr->flags |= flag; \
2100 return instr; \
2114 struct ir3_instruction *instr = \
2117 __ssa_dst(instr); \
2118 __ssa_src(instr, a, aflags); \
2119 __ssa_src(instr, b, bflags); \
2120 __ssa_src(instr, c, cflags); \
2121 instr->flags |= flag; \
2122 return instr; \
2136 struct ir3_instruction *instr = \
2139 __ssa_dst(instr); \
2140 __ssa_src(instr, a, aflags); \
2141 __ssa_src(instr, b, bflags); \
2142 __ssa_src(instr, c, cflags); \
2143 __ssa_src(instr, d, dflags); \
2144 instr->flags |= flag; \
2145 return instr; \
2160 struct ir3_instruction *instr = ir3_instr_create(block, opc, 1, 5); \
2161 __ssa_dst(instr); \
2162 __ssa_src(instr, a, aflags); \
2163 __ssa_src(instr, b, bflags); \
2164 __ssa_src(instr, c, cflags); \
2165 __ssa_src(instr, d, dflags); \
2166 __ssa_src(instr, e, eflags); \
2167 instr->flags |= flag; \
2168 return instr; \
2183 struct ir3_instruction *instr = ir3_instr_create(block, opc, 1, 6); \
2185 __ssa_dst(instr); \
2186 __ssa_src(instr, a, aflags); \
2187 __ssa_src(instr, b, bflags); \
2188 __ssa_src(instr, c, cflags); \
2189 __ssa_src(instr, d, dflags); \
2190 __ssa_src(instr, e, eflags); \
2191 __ssa_src(instr, f, fflags); \
2192 instr->flags |= flag; \
2193 return instr; \
2224 struct ir3_instruction *instr =
2226 __ssa_dst(instr);
2227 return instr;
2233 struct ir3_instruction *instr =
2235 __ssa_dst(instr);
2236 return instr;