Lines Matching defs:layout
165 const struct fdl_layout *layout = layouts[0];
166 uint32_t width = u_minify(layout->width0, args->base_miplevel);
167 uint32_t height = u_minify(layout->height0, args->base_miplevel);
174 if (util_format_get_blockwidth(layout->format) > 1 &&
176 width = util_format_get_nblocksx(layout->format, width);
177 } else if (util_format_get_blockwidth(layout->format) == 1 &&
182 if (util_format_get_blockheight(layout->format) > 1 &&
184 height = util_format_get_nblocksy(layout->format, height);
185 } else if (util_format_get_blockheight(layout->format) == 1 &&
192 storage_depth = u_minify(layout->depth0, args->base_miplevel);
204 fdl_surface_offset(layout, args->base_miplevel, args->base_array_layer);
206 fdl_ubwc_offset(layout, args->base_miplevel, args->base_array_layer);
208 uint32_t pitch = fdl_pitch(layout, args->base_miplevel);
209 uint32_t ubwc_pitch = fdl_ubwc_pitch(layout, args->base_miplevel);
210 uint32_t layer_size = fdl_layer_stride(layout, args->base_miplevel);
213 fd6_texture_format(args->format, layout->tile_mode);
215 fd6_texture_swap(args->format, layout->tile_mode);
216 enum a6xx_tile_mode tile_mode = fdl_tile_mode(layout, args->base_miplevel);
218 bool ubwc_enabled = fdl_ubwc_enabled(layout, args->base_miplevel);
248 A6XX_TEX_CONST_0_SAMPLES(util_logbase2(layout->nr_samples)) |
254 A6XX_TEX_CONST_2_PITCHALIGN(layout->pitchalign - 6) |
262 if (layout->tile_all)
279 /* no separate ubwc base, image must have the expected layout */
306 fdl6_get_ubwc_blockwidth(layout, &block_width, &block_height);
311 view->descriptor[9] |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
320 A6XX_TEX_CONST_3_MIN_LAYERSZ(layout->slices[layout->mip_levels - 1].size0);
324 layout->nr_samples > 1 &&
334 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(util_logbase2(layout->nr_samples)) |
347 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
361 view->ubwc_layer_size = layout->ubwc_layer_size;
364 fd6_color_format(args->format, layout->tile_mode);
373 fd6_color_swap(args->format, layout->tile_mode);
401 tile_mode == TILE6_LINEAR && args->base_miplevel != layout->mip_levels - 1;
424 A6XX_RB_BLIT_DST_INFO_SAMPLES(util_logbase2(layout->nr_samples)) |