Lines Matching defs:REG
351 r = regbase("CP_SCRATCH[0].REG");
540 #define REG(x, fxn) { #x, fxn }
549 REG(CP_SCRATCH_REG0, reg_dump_scratch),
550 REG(CP_SCRATCH_REG1, reg_dump_scratch),
551 REG(CP_SCRATCH_REG2, reg_dump_scratch),
552 REG(CP_SCRATCH_REG3, reg_dump_scratch),
553 REG(CP_SCRATCH_REG4, reg_dump_scratch),
554 REG(CP_SCRATCH_REG5, reg_dump_scratch),
555 REG(CP_SCRATCH_REG6, reg_dump_scratch),
556 REG(CP_SCRATCH_REG7, reg_dump_scratch),
559 REG(CP_SCRATCH_REG0, reg_dump_scratch),
560 REG(CP_SCRATCH_REG1, reg_dump_scratch),
561 REG(CP_SCRATCH_REG2, reg_dump_scratch),
562 REG(CP_SCRATCH_REG3, reg_dump_scratch),
563 REG(CP_SCRATCH_REG4, reg_dump_scratch),
564 REG(CP_SCRATCH_REG5, reg_dump_scratch),
565 REG(CP_SCRATCH_REG6, reg_dump_scratch),
566 REG(CP_SCRATCH_REG7, reg_dump_scratch),
567 REG(VSC_SIZE_ADDRESS, reg_dump_gpuaddr),
568 REG(SP_VS_PVT_MEM_ADDR_REG, reg_dump_gpuaddr),
569 REG(SP_FS_PVT_MEM_ADDR_REG, reg_dump_gpuaddr),
570 REG(SP_VS_OBJ_START_REG, reg_disasm_gpuaddr),
571 REG(SP_FS_OBJ_START_REG, reg_disasm_gpuaddr),
572 REG(TPL1_TP_FS_BORDER_COLOR_BASE_ADDR, reg_dump_gpuaddr),
575 REG(CP_SCRATCH[0].REG, reg_dump_scratch),
576 REG(CP_SCRATCH[0x1].REG, reg_dump_scratch),
577 REG(CP_SCRATCH[0x2].REG, reg_dump_scratch),
578 REG(CP_SCRATCH[0x3].REG, reg_dump_scratch),
579 REG(CP_SCRATCH[0x4].REG, reg_dump_scratch),
580 REG(CP_SCRATCH[0x5].REG, reg_dump_scratch),
581 REG(CP_SCRATCH[0x6].REG, reg_dump_scratch),
582 REG(CP_SCRATCH[0x7].REG, reg_dump_scratch),
583 REG(SP_VS_PVT_MEM_ADDR, reg_dump_gpuaddr),
584 REG(SP_FS_PVT_MEM_ADDR, reg_dump_gpuaddr),
585 REG(SP_GS_PVT_MEM_ADDR, reg_dump_gpuaddr),
586 REG(SP_HS_PVT_MEM_ADDR, reg_dump_gpuaddr),
587 REG(SP_DS_PVT_MEM_ADDR, reg_dump_gpuaddr),
588 REG(SP_CS_PVT_MEM_ADDR, reg_dump_gpuaddr),
589 REG(SP_VS_OBJ_START, reg_disasm_gpuaddr),
590 REG(SP_FS_OBJ_START, reg_disasm_gpuaddr),
591 REG(SP_GS_OBJ_START, reg_disasm_gpuaddr),
592 REG(SP_HS_OBJ_START, reg_disasm_gpuaddr),
593 REG(SP_DS_OBJ_START, reg_disasm_gpuaddr),
594 REG(SP_CS_OBJ_START, reg_disasm_gpuaddr),
595 REG(TPL1_TP_VS_BORDER_COLOR_BASE_ADDR, reg_dump_gpuaddr),
596 REG(TPL1_TP_HS_BORDER_COLOR_BASE_ADDR, reg_dump_gpuaddr),
597 REG(TPL1_TP_DS_BORDER_COLOR_BASE_ADDR, reg_dump_gpuaddr),
598 REG(TPL1_TP_GS_BORDER_COLOR_BASE_ADDR, reg_dump_gpuaddr),
599 REG(TPL1_TP_FS_BORDER_COLOR_BASE_ADDR, reg_dump_gpuaddr),
602 REG(CP_SCRATCH[0x4].REG, reg_dump_scratch),
603 REG(CP_SCRATCH[0x5].REG, reg_dump_scratch),
604 REG(CP_SCRATCH[0x6].REG, reg_dump_scratch),
605 REG(CP_SCRATCH[0x7].REG, reg_dump_scratch),
606 REG(SP_VS_OBJ_START_LO, reg_gpuaddr_lo),
607 REG(SP_VS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
608 REG(SP_HS_OBJ_START_LO, reg_gpuaddr_lo),
609 REG(SP_HS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
610 REG(SP_DS_OBJ_START_LO, reg_gpuaddr_lo),
611 REG(SP_DS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
612 REG(SP_GS_OBJ_START_LO, reg_gpuaddr_lo),
613 REG(SP_GS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
614 REG(SP_FS_OBJ_START_LO, reg_gpuaddr_lo),
615 REG(SP_FS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
616 REG(SP_CS_OBJ_START_LO, reg_gpuaddr_lo),
617 REG(SP_CS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
618 REG(TPL1_VS_TEX_CONST_LO, reg_gpuaddr_lo),
619 REG(TPL1_VS_TEX_CONST_HI, reg_dump_tex_const_hi),
620 REG(TPL1_VS_TEX_SAMP_LO, reg_gpuaddr_lo),
621 REG(TPL1_VS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
622 REG(TPL1_HS_TEX_CONST_LO, reg_gpuaddr_lo),
623 REG(TPL1_HS_TEX_CONST_HI, reg_dump_tex_const_hi),
624 REG(TPL1_HS_TEX_SAMP_LO, reg_gpuaddr_lo),
625 REG(TPL1_HS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
626 REG(TPL1_DS_TEX_CONST_LO, reg_gpuaddr_lo),
627 REG(TPL1_DS_TEX_CONST_HI, reg_dump_tex_const_hi),
628 REG(TPL1_DS_TEX_SAMP_LO, reg_gpuaddr_lo),
629 REG(TPL1_DS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
630 REG(TPL1_GS_TEX_CONST_LO, reg_gpuaddr_lo),
631 REG(TPL1_GS_TEX_CONST_HI, reg_dump_tex_const_hi),
632 REG(TPL1_GS_TEX_SAMP_LO, reg_gpuaddr_lo),
633 REG(TPL1_GS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
634 REG(TPL1_FS_TEX_CONST_LO, reg_gpuaddr_lo),
635 REG(TPL1_FS_TEX_CONST_HI, reg_dump_tex_const_hi),
636 REG(TPL1_FS_TEX_SAMP_LO, reg_gpuaddr_lo),
637 REG(TPL1_FS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
638 REG(TPL1_CS_TEX_CONST_LO, reg_gpuaddr_lo),
639 REG(TPL1_CS_TEX_CONST_HI, reg_dump_tex_const_hi),
640 REG(TPL1_CS_TEX_SAMP_LO, reg_gpuaddr_lo),
641 REG(TPL1_CS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
642 REG(TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, reg_gpuaddr_lo),
643 REG(TPL1_TP_BORDER_COLOR_BASE_ADDR_HI, reg_dump_gpuaddr_hi),
644 // REG(RB_MRT_FLAG_BUFFER[0].ADDR_LO, reg_gpuaddr_lo),
645 // REG(RB_MRT_FLAG_BUFFER[0].ADDR_HI, reg_dump_gpuaddr_hi),
646 // REG(RB_MRT_FLAG_BUFFER[1].ADDR_LO, reg_gpuaddr_lo),
647 // REG(RB_MRT_FLAG_BUFFER[1].ADDR_HI, reg_dump_gpuaddr_hi),
648 // REG(RB_MRT_FLAG_BUFFER[2].ADDR_LO, reg_gpuaddr_lo),
649 // REG(RB_MRT_FLAG_BUFFER[2].ADDR_HI, reg_dump_gpuaddr_hi),
650 // REG(RB_MRT_FLAG_BUFFER[3].ADDR_LO, reg_gpuaddr_lo),
651 // REG(RB_MRT_FLAG_BUFFER[3].ADDR_HI, reg_dump_gpuaddr_hi),
652 // REG(RB_MRT_FLAG_BUFFER[4].ADDR_LO, reg_gpuaddr_lo),
653 // REG(RB_MRT_FLAG_BUFFER[4].ADDR_HI, reg_dump_gpuaddr_hi),
654 // REG(RB_MRT_FLAG_BUFFER[5].ADDR_LO, reg_gpuaddr_lo),
655 // REG(RB_MRT_FLAG_BUFFER[5].ADDR_HI, reg_dump_gpuaddr_hi),
656 // REG(RB_MRT_FLAG_BUFFER[6].ADDR_LO, reg_gpuaddr_lo),
657 // REG(RB_MRT_FLAG_BUFFER[6].ADDR_HI, reg_dump_gpuaddr_hi),
658 // REG(RB_MRT_FLAG_BUFFER[7].ADDR_LO, reg_gpuaddr_lo),
659 // REG(RB_MRT_FLAG_BUFFER[7].ADDR_HI, reg_dump_gpuaddr_hi),
660 // REG(RB_BLIT_FLAG_DST_LO, reg_gpuaddr_lo),
661 // REG(RB_BLIT_FLAG_DST_HI, reg_dump_gpuaddr_hi),
662 // REG(RB_MRT[0].BASE_LO, reg_gpuaddr_lo),
663 // REG(RB_MRT[0].BASE_HI, reg_dump_gpuaddr_hi),
664 // REG(RB_DEPTH_BUFFER_BASE_LO, reg_gpuaddr_lo),
665 // REG(RB_DEPTH_BUFFER_BASE_HI, reg_dump_gpuaddr_hi),
666 // REG(RB_DEPTH_FLAG_BUFFER_BASE_LO, reg_gpuaddr_lo),
667 // REG(RB_DEPTH_FLAG_BUFFER_BASE_HI, reg_dump_gpuaddr_hi),
668 // REG(RB_BLIT_DST_LO, reg_gpuaddr_lo),
669 // REG(RB_BLIT_DST_HI, reg_dump_gpuaddr_hi),
671 // REG(RB_2D_SRC_LO, reg_gpuaddr_lo),
672 // REG(RB_2D_SRC_HI, reg_dump_gpuaddr_hi),
673 // REG(RB_2D_SRC_FLAGS_LO, reg_gpuaddr_lo),
674 // REG(RB_2D_SRC_FLAGS_HI, reg_dump_gpuaddr_hi),
675 // REG(RB_2D_DST_LO, reg_gpuaddr_lo),
676 // REG(RB_2D_DST_HI, reg_dump_gpuaddr_hi),
677 // REG(RB_2D_DST_FLAGS_LO, reg_gpuaddr_lo),
678 // REG(RB_2D_DST_FLAGS_HI, reg_dump_gpuaddr_hi),
682 REG(CP_SCRATCH[0x4].REG, reg_dump_scratch),
683 REG(CP_SCRATCH[0x5].REG, reg_dump_scratch),
684 REG(CP_SCRATCH[0x6].REG, reg_dump_scratch),
685 REG(CP_SCRATCH[0x7].REG, reg_dump_scratch),