Lines Matching defs:val
40 uint32_t val[EMU_NUM_GPR_REGS];
48 uint32_t val[EMU_NUM_CONTROL_REGS];
55 uint32_t val[EMU_NUM_GPU_REGS];
62 uint32_t val[EMU_NUM_PIPE_REGS];
75 emu_queue_push(struct emu_queue *q, uint32_t val)
84 q->fifo[q->head] = val;
90 emu_queue_pop(struct emu_queue *q, uint32_t *val)
99 *val = q->fifo[q->tail];
235 void emu_mem_write_dword(struct emu *emu, uintptr_t gpuaddr, uint32_t val);
244 void emu_set_gpr_reg(struct emu *emu, unsigned n, uint32_t val);
246 void emu_set_gpu_reg(struct emu *emu, unsigned n, uint32_t val);
249 void emu_set_control_reg(struct emu *emu, unsigned n, uint32_t val);
256 * val = emu_get_reg32(emu, &SOME_REG);
278 void emu_set_reg32(struct emu *emu, struct emu_reg *reg, uint32_t val);
279 void emu_set_reg64(struct emu *emu, struct emu_reg *reg, uint64_t val);
283 void emu_set_draw_state_reg(struct emu *emu, unsigned n, uint32_t val);