Lines Matching refs:emu
37 #include "emu.h"
51 emu_alu(struct emu *emu, afuc_opc opc, uint32_t src1, uint32_t src2)
57 emu->carry = tmp >> 32;
60 return src1 + src2 + emu->carry;
63 emu->carry = tmp >> 32;
66 return src1 - src2 + emu->carry;
112 load_store_addr(struct emu *emu, unsigned gpr)
116 uintptr_t addr = emu_get_reg32(emu, &LOAD_STORE_HI);
119 return addr + emu_get_gpr_reg(emu, gpr);
123 emu_instr(struct emu *emu, afuc_instr *instr)
125 uint32_t rem = emu_get_gpr_reg(emu, REG_REM);
135 uint32_t val = emu_alu(emu, opc,
136 emu_get_gpr_reg(emu, instr->alui.src),
138 emu_set_gpr_reg(emu, instr->alui.dst, val);
143 emu_set_gpr_reg(emu, instr->movi.dst, val);
147 uint32_t val = emu_alu(emu, instr->alu.alu,
148 emu_get_gpr_reg(emu, instr->alu.src1),
149 emu_get_gpr_reg(emu, instr->alu.src2));
150 emu_set_gpr_reg(emu, instr->alu.dst, val);
158 emu_set_gpr_reg(emu, REG_REM, --rem);
159 emu_dump_state_change(emu);
160 emu_set_gpr_reg(emu, REG_DATA,
161 emu_get_gpr_reg(emu, instr->alu.src2));
163 emu_set_gpr_reg(emu, REG_REM, --rem);
164 emu_dump_state_change(emu);
165 emu_set_gpr_reg(emu, REG_DATA,
166 emu_get_gpr_reg(emu, instr->alu.src2));
167 emu_set_gpr_reg(emu, REG_REM, --rem);
168 emu_dump_state_change(emu);
169 emu_set_gpr_reg(emu, REG_DATA,
170 emu_get_gpr_reg(emu, instr->alu.src2));
172 emu_set_gpr_reg(emu, REG_REM, --rem);
173 emu_dump_state_change(emu);
174 emu_set_gpr_reg(emu, REG_DATA,
175 emu_get_gpr_reg(emu, instr->alu.src2));
176 emu_set_gpr_reg(emu, REG_REM, --rem);
177 emu_dump_state_change(emu);
178 emu_set_gpr_reg(emu, instr->alu.dst,
179 emu_get_gpr_reg(emu, instr->alu.src2));
180 emu_set_gpr_reg(emu, REG_REM, --rem);
181 emu_dump_state_change(emu);
182 emu_set_gpr_reg(emu, REG_DATA,
183 emu_get_gpr_reg(emu, instr->alu.src2));
189 uint32_t src1 = emu_get_gpr_reg(emu, instr->control.src1);
190 uint32_t src2 = emu_get_gpr_reg(emu, instr->control.src2);
193 emu_set_gpr_reg(emu, instr->control.src2, src2 + instr->control.uimm);
194 } else if (instr->control.flags && !emu->quiet) {
198 emu_set_control_reg(emu, src2 + instr->control.uimm, src1);
202 uint32_t src2 = emu_get_gpr_reg(emu, instr->control.src2);
205 emu_set_gpr_reg(emu, instr->control.src2, src2 + instr->control.uimm);
206 } else if (instr->control.flags && !emu->quiet) {
210 emu_set_gpr_reg(emu, instr->control.src1,
211 emu_get_control_reg(emu, src2 + instr->control.uimm));
215 uintptr_t addr = load_store_addr(emu, instr->control.src2) +
219 uint32_t src2 = emu_get_gpr_reg(emu, instr->control.src2);
220 emu_set_gpr_reg(emu, instr->control.src2, src2 + instr->control.uimm);
221 } else if (instr->control.flags && !emu->quiet) {
225 uint32_t val = emu_mem_read_dword(emu, addr);
227 emu_set_gpr_reg(emu, instr->control.src1, val);
232 uintptr_t addr = load_store_addr(emu, instr->control.src2) +
236 uint32_t src2 = emu_get_gpr_reg(emu, instr->control.src2);
237 emu_set_gpr_reg(emu, instr->control.src2, src2 + instr->control.uimm);
238 } else if (instr->control.flags && !emu->quiet) {
242 uint32_t val = emu_get_gpr_reg(emu, instr->control.src1);
244 emu_mem_write_dword(emu, addr, val);
249 uint32_t off = emu->gpr_regs.pc + instr->br.ioff;
250 uint32_t src = emu_get_gpr_reg(emu, instr->br.src);
254 emu->branch_target = off;
257 emu->branch_target = off;
260 emu->branch_target = off;
263 emu->branch_target = off;
270 assert(emu->call_stack_idx > 0);
273 emu->branch_target = emu->call_stack[--emu->call_stack_idx];
278 assert(emu->call_stack_idx < ARRAY_SIZE(emu->call_stack));
283 emu->call_stack[emu->call_stack_idx++] = emu->gpr_regs.pc + 2;
284 emu->branch_target = instr->call.uoff;
289 assert(!emu->branch_target);
290 emu->run_mode = false;
291 emu->waitin = true;
307 emu_set_gpr_reg(emu, REG_REM, --rem);
312 emu_step(struct emu *emu)
314 afuc_instr *instr = (void *)&emu->instrs[emu->gpr_regs.pc];
318 emu_main_prompt(emu);
320 uint32_t branch_target = emu->branch_target;
321 emu->branch_target = 0;
323 bool waitin = emu->waitin;
324 emu->waitin = false;
330 if (!emu_get_gpr_reg(emu, REG_REM))
333 emu_clear_state_change(emu);
334 emu_instr(emu, instr);
339 if (emu_get_gpr_reg(emu, REG_REM))
340 emu_dump_state_change(emu);
343 emu_clear_state_change(emu);
344 emu_instr(emu, instr);
347 emu->gpr_regs.pc++;
350 emu->gpr_regs.pc = branch_target;
354 uint32_t hdr = emu_get_gpr_reg(emu, 1);
367 emu->gpr_regs.val[1] &= 0x0fffffff;
376 assert(id < ARRAY_SIZE(emu->jmptbl));
378 emu_set_gpr_reg(emu, REG_REM, count);
379 emu->gpr_regs.pc = emu->jmptbl[id];
382 emu_dump_state_change(emu);
386 emu_run_bootstrap(struct emu *emu)
390 emu->quiet = true;
391 emu->run_mode = true;
393 while (emu_get_reg32(emu, &PACKET_TABLE_WRITE_ADDR) < 0x80) {
394 emu_step(emu);
400 check_access(struct emu *emu, uintptr_t gpuaddr, unsigned sz)
414 emu_mem_read_dword(struct emu *emu, uintptr_t gpuaddr)
416 check_access(emu, gpuaddr, 4);
417 return *(uint32_t *)(emu->gpumem + gpuaddr);
421 mem_write_dword(struct emu *emu, uintptr_t gpuaddr, uint32_t val)
423 check_access(emu, gpuaddr, 4);
424 *(uint32_t *)(emu->gpumem + gpuaddr) = val;
428 emu_mem_write_dword(struct emu *emu, uintptr_t gpuaddr, uint32_t val)
430 mem_write_dword(emu, gpuaddr, val);
431 assert(emu->gpumem_written == ~0);
432 emu->gpumem_written = gpuaddr;
436 emu_init(struct emu *emu)
438 emu->gpumem = mmap(NULL, EMU_MEMORY_SIZE,
442 if (emu->gpumem == MAP_FAILED) {
448 for (unsigned i = 0; i < emu->sizedwords; i++) {
449 mem_write_dword(emu, EMU_INSTR_BASE + (4 * i), emu->instrs[i]);
456 if (emu->lpac) {
457 emu_set_reg64(emu, &CP_LPAC_SQE_INSTR_BASE, EMU_INSTR_BASE);
459 emu_set_reg64(emu, &CP_SQE_INSTR_BASE, EMU_INSTR_BASE);
462 if (emu->gpu_id == 660) {
463 emu_set_control_reg(emu, 0, 3 << 28);
464 } else if (emu->gpu_id == 650) {
465 emu_set_control_reg(emu, 0, 1 << 28);
470 emu_fini(struct emu *emu)
472 uint32_t *instrs = emu->instrs;
473 unsigned sizedwords = emu->sizedwords;
474 unsigned gpu_id = emu->gpu_id;
476 munmap(emu->gpumem, EMU_MEMORY_SIZE);
477 memset(emu, 0, sizeof(*emu));
479 emu->instrs = instrs;
480 emu->sizedwords = sizedwords;
481 emu->gpu_id = gpu_id;