Lines Matching defs:options
66 const nir_lower_subgroups_options *options)
73 return nir_extract_bits(b, &value, 1, 0, options->ballot_components,
74 options->ballot_bit_size);
202 const nir_lower_subgroups_options *options)
218 if (options->lower_to_scalar && swizzle->num_components > 1) {
219 return lower_subgroup_op_to_scalar(b, swizzle, options->lower_shuffle_to_32bit);
220 } else if (options->lower_shuffle_to_32bit && swizzle->src[0].ssa->bit_size == 64) {
232 const nir_lower_subgroups_options *options)
235 options->lower_shuffle_to_swizzle_amd &&
238 lower_shuffle_to_swizzle(b, intrin, options);
297 bool lower_to_32bit = options->lower_shuffle_to_32bit && is_shuffle;
298 if (options->lower_to_scalar && shuffle->num_components > 1) {
397 const nir_lower_subgroups_options *options)
404 nir_ishl(b, nir_imm_intN_t(b, val, options->ballot_bit_size), shift);
406 if (options->ballot_components == 1)
424 for (unsigned i = 0; i < options->ballot_components; i++)
425 min_shift[i].i32 = i * options->ballot_bit_size;
426 nir_ssa_def *min_shift_val = nir_build_imm(b, options->ballot_components, 32, min_shift);
429 for (unsigned i = 0; i < options->ballot_components; i++)
430 max_shift[i].i32 = (i + 1) * options->ballot_bit_size;
431 nir_ssa_def *max_shift_val = nir_build_imm(b, options->ballot_components, 32, max_shift);
442 const nir_lower_subgroups_options *options)
446 return build_ballot_imm_ishl(b, 1, subgroup_idx, options);
451 const nir_lower_subgroups_options *options)
455 return build_ballot_imm_ishl(b, ~0ull, subgroup_idx, options);
460 const nir_lower_subgroups_options *options)
464 return build_ballot_imm_ishl(b, ~1ull, subgroup_idx, options);
474 const nir_lower_subgroups_options *options)
480 nir_ushr(b, nir_imm_intN_t(b, ~0ull, options->ballot_bit_size),
481 nir_isub_imm(b, options->ballot_bit_size,
505 for (unsigned i = 0; i < options->ballot_components; i++)
506 min_idx[i].i32 = i * options->ballot_bit_size;
507 nir_ssa_def *min_idx_val = nir_build_imm(b, options->ballot_components, 32, min_idx);
510 nir_pad_vector_imm_int(b, result, ~0ull, options->ballot_components);
513 result_extended, nir_imm_intN_t(b, 0, options->ballot_bit_size));
558 const nir_lower_subgroups_options *options)
560 if (!options->lower_quad_broadcast_dynamic_to_const)
561 return lower_to_shuffle(b, intrin, options);
578 if (options->lower_to_scalar && qbcst->num_components > 1) {
608 const nir_lower_subgroups_options *options = _options;
614 if (options->lower_vote_trivial)
620 if (options->lower_vote_trivial)
623 if (options->lower_vote_eq)
626 if (options->lower_to_scalar && intrin->num_components > 1)
631 if (options->subgroup_size)
632 return nir_imm_int(b, options->subgroup_size);
636 if (options->lower_to_scalar && intrin->num_components > 1)
639 if (options->lower_read_invocation_to_cond)
645 if (options->lower_to_scalar && intrin->num_components > 1)
654 if (!options->lower_subgroup_masks)
660 val = build_subgroup_eq_mask(b, options);
663 val = nir_iand(b, build_subgroup_ge_mask(b, options),
664 build_subgroup_mask(b, options));
667 val = nir_iand(b, build_subgroup_gt_mask(b, options),
668 build_subgroup_mask(b, options));
671 val = nir_inot(b, build_subgroup_gt_mask(b, options));
674 val = nir_inot(b, build_subgroup_ge_mask(b, options));
686 if (intrin->dest.ssa.num_components == options->ballot_components &&
687 intrin->dest.ssa.bit_size == options->ballot_bit_size)
691 nir_ballot(b, options->ballot_components, options->ballot_bit_size,
705 options);
728 int_val = nir_iand(b, int_val, build_subgroup_mask(b, options));
762 mask = nir_inot(b, build_subgroup_gt_mask(b, options));
764 mask = nir_inot(b, build_subgroup_ge_mask(b, options));
769 options);
775 if (!options->lower_elect)
782 if (options->lower_shuffle)
784 else if (options->lower_to_scalar && intrin->num_components > 1)
785 return lower_subgroup_op_to_scalar(b, intrin, options->lower_shuffle_to_32bit);
786 else if (options->lower_shuffle_to_32bit && intrin->src[0].ssa->bit_size == 64)
792 if (options->lower_relative_shuffle)
793 return lower_to_shuffle(b, intrin, options);
794 else if (options->lower_to_scalar && intrin->num_components > 1)
795 return lower_subgroup_op_to_scalar(b, intrin, options->lower_shuffle_to_32bit);
796 else if (options->lower_shuffle_to_32bit && intrin->src[0].ssa->bit_size == 64)
804 if (options->lower_quad ||
805 (options->lower_quad_broadcast_dynamic &&
808 return lower_dynamic_quad_broadcast(b, intrin, options);
809 else if (options->lower_to_scalar && intrin->num_components > 1)
816 if (options->subgroup_size &&
817 nir_intrinsic_cluster_size(intrin) >= options->subgroup_size) {
821 if (options->lower_to_scalar && intrin->num_components > 1)
827 if (options->lower_to_scalar && intrin->num_components > 1)
840 const nir_lower_subgroups_options *options)
845 (void *)options);