Lines Matching refs:buffer
107 uint32_t buffer)
117 load.buffer_to_load = buffer;
127 * buffer, we need to use the underlying DS format.
129 if (buffer == ZSTENCIL &&
304 uint32_t buffer,
318 store.buffer_to_store = buffer;
329 * buffer, we need to use the underlying DS format.
331 if (buffer == ZSTENCIL &&
530 /* GFXH-1689: The per-buffer store command's clear buffer bit is broken
544 * the per-buffer store clear bit, even if we need to store the buffers,
550 * using the clear buffer bit in depth/stencil stores works fine.
601 * that we must not request a tile buffer clear here in that case, since
602 * that would clear the tile buffer before we get to emit the actual
647 /* If we have any depth/stencil clears we can't use the per-buffer clear
790 * if we are recording a secondary command buffer. In that case, we will
792 * buffer.
1449 /* GFXH-1918: the early-z buffer may load incorrect depth values
1471 perf_debug("Loading depth aspect in a secondary command buffer "
2032 assert(c_vb->buffer->mem->bo);
2033 attr.address = v3dv_cl_address(c_vb->buffer->mem->bo,
2034 c_vb->buffer->mem_offset +
2177 * have a valid index buffer before attempting to emit state for it.
2180 v3dv_buffer_from_handle(cmd_buffer->state.index_buffer.buffer);
2254 struct v3dv_buffer *buffer,
2273 prim.address = v3dv_cl_address(buffer->mem->bo,
2274 buffer->mem_offset + offset);
2280 struct v3dv_buffer *buffer,
2302 prim.address = v3dv_cl_address(buffer->mem->bo,
2303 buffer->mem_offset + offset);