Lines Matching refs:instr
741 struct v3d_qpu_instr *instr)
764 instr->alu.add.op = desc->op;
770 if (instr->alu.add.op == V3D_QPU_A_FMIN)
771 instr->alu.add.op = V3D_QPU_A_FMAX;
772 if (instr->alu.add.op == V3D_QPU_A_FADD)
773 instr->alu.add.op = V3D_QPU_A_FADDNF;
779 switch (instr->alu.add.op) {
785 instr->alu.add.op = V3D_QPU_A_STVPMV;
788 instr->alu.add.op = V3D_QPU_A_STVPMD;
791 instr->alu.add.op = V3D_QPU_A_STVPMP;
801 switch (instr->alu.add.op) {
809 if (instr->alu.add.op != V3D_QPU_A_VFPACK)
810 instr->alu.add.output_pack = (op >> 4) & 0x3;
812 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
815 &instr->alu.add.a_unpack)) {
820 &instr->alu.add.b_unpack)) {
831 instr->alu.add.output_pack = mux_b & 0x3;
834 &instr->alu.add.a_unpack)) {
843 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
846 &instr->alu.add.a_unpack)) {
854 &instr->alu.add.a_unpack)) {
858 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
859 instr->alu.add.b_unpack = V3D_QPU_UNPACK_NONE;
863 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
864 instr->alu.add.a_unpack = V3D_QPU_UNPACK_NONE;
865 instr->alu.add.b_unpack = V3D_QPU_UNPACK_NONE;
869 instr->alu.add.a = mux_a;
870 instr->alu.add.b = mux_b;
871 instr->alu.add.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
873 instr->alu.add.magic_write = false;
875 switch (instr->alu.add.op) {
877 instr->alu.add.op = V3D_QPU_A_LDVPMV_OUT;
880 instr->alu.add.op = V3D_QPU_A_LDVPMD_OUT;
883 instr->alu.add.op = V3D_QPU_A_LDVPMG_OUT;
886 instr->alu.add.magic_write = true;
896 struct v3d_qpu_instr *instr)
910 instr->alu.mul.op = desc->op;
913 switch (instr->alu.mul.op) {
915 instr->alu.mul.output_pack = ((op >> 4) & 0x3) - 1;
918 &instr->alu.mul.a_unpack)) {
923 &instr->alu.mul.b_unpack)) {
930 instr->alu.mul.output_pack = (((op & 1) << 1) +
934 &instr->alu.mul.a_unpack)) {
941 instr->alu.mul.output_pack = V3D_QPU_PACK_NONE;
944 &instr->alu.mul.a_unpack)) {
948 instr->alu.mul.b_unpack = V3D_QPU_UNPACK_NONE;
953 instr->alu.mul.output_pack = V3D_QPU_PACK_NONE;
954 instr->alu.mul.a_unpack = V3D_QPU_UNPACK_NONE;
955 instr->alu.mul.b_unpack = V3D_QPU_UNPACK_NONE;
959 instr->alu.mul.a = mux_a;
960 instr->alu.mul.b = mux_b;
961 instr->alu.mul.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_M);
962 instr->alu.mul.magic_write = packed_inst & V3D_QPU_MM;
989 const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
991 uint32_t waddr = instr->alu.add.waddr;
992 uint32_t mux_a = instr->alu.add.a;
993 uint32_t mux_b = instr->alu.add.b;
994 int nsrc = v3d_qpu_add_op_num_src(instr->alu.add.op);
997 instr->alu.add.op);
1015 switch (instr->alu.add.op) {
1033 assert(!instr->alu.add.magic_write);
1039 assert(!instr->alu.add.magic_write);
1047 switch (instr->alu.add.op) {
1058 if (!v3d_qpu_float32_pack_pack(instr->alu.add.output_pack,
1064 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1069 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.b_unpack,
1078 if (((instr->alu.add.op == V3D_QPU_A_FMIN ||
1079 instr->alu.add.op == V3D_QPU_A_FADD) && ordering) ||
1080 ((instr->alu.add.op == V3D_QPU_A_FMAX ||
1081 instr->alu.add.op == V3D_QPU_A_FADDNF) && !ordering)) {
1103 if (instr->alu.add.a_unpack == V3D_QPU_UNPACK_ABS ||
1104 instr->alu.add.b_unpack == V3D_QPU_UNPACK_ABS) {
1108 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1113 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.b_unpack,
1132 if (!v3d_qpu_float32_pack_pack(instr->alu.add.output_pack,
1138 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1152 if (instr->alu.add.output_pack != V3D_QPU_PACK_NONE)
1156 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1168 if (instr->alu.add.output_pack != V3D_QPU_PACK_NONE ||
1169 instr->alu.add.b_unpack != V3D_QPU_UNPACK_NONE) {
1173 if (!v3d_qpu_float16_unpack_pack(instr->alu.add.a_unpack,
1181 if (instr->alu.add.op != V3D_QPU_A_NOP &&
1182 (instr->alu.add.output_pack != V3D_QPU_PACK_NONE ||
1183 instr->alu.add.a_unpack != V3D_QPU_UNPACK_NONE ||
1184 instr->alu.add.b_unpack != V3D_QPU_UNPACK_NONE)) {
1194 if (instr->alu.add.magic_write && !no_magic_write)
1202 const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
1204 uint32_t mux_a = instr->alu.mul.a;
1205 uint32_t mux_b = instr->alu.mul.b;
1206 int nsrc = v3d_qpu_mul_op_num_src(instr->alu.mul.op);
1210 instr->alu.mul.op);
1226 switch (instr->alu.mul.op) {
1230 if (!v3d_qpu_float32_pack_pack(instr->alu.mul.output_pack,
1239 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.a_unpack,
1245 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.b_unpack,
1256 if (!v3d_qpu_float32_pack_pack(instr->alu.mul.output_pack,
1263 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.a_unpack,
1274 if (instr->alu.mul.output_pack != V3D_QPU_PACK_NONE)
1277 if (!v3d_qpu_float16_unpack_pack(instr->alu.mul.a_unpack,
1281 if (instr->alu.mul.a_unpack == V3D_QPU_UNPACK_SWAP_16)
1286 if (instr->alu.mul.b_unpack != V3D_QPU_UNPACK_NONE)
1300 *packed_instr |= QPU_SET_FIELD(instr->alu.mul.waddr, V3D_QPU_WADDR_M);
1301 if (instr->alu.mul.magic_write)
1310 struct v3d_qpu_instr *instr)
1312 instr->type = V3D_QPU_INSTR_TYPE_ALU;
1316 &instr->sig))
1320 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig)) {
1321 instr->sig_addr = packed_cond & ~V3D_QPU_COND_SIG_MAGIC_ADDR;
1322 instr->sig_magic = packed_cond & V3D_QPU_COND_SIG_MAGIC_ADDR;
1324 instr->flags.ac = V3D_QPU_COND_NONE;
1325 instr->flags.mc = V3D_QPU_COND_NONE;
1326 instr->flags.apf = V3D_QPU_PF_NONE;
1327 instr->flags.mpf = V3D_QPU_PF_NONE;
1328 instr->flags.auf = V3D_QPU_UF_NONE;
1329 instr->flags.muf = V3D_QPU_UF_NONE;
1331 if (!v3d_qpu_flags_unpack(devinfo, packed_cond, &instr->flags))
1335 instr->raddr_a = QPU_GET_FIELD(packed_instr, V3D_QPU_RADDR_A);
1336 instr->raddr_b = QPU_GET_FIELD(packed_instr, V3D_QPU_RADDR_B);
1338 if (!v3d_qpu_add_unpack(devinfo, packed_instr, instr))
1341 if (!v3d_qpu_mul_unpack(devinfo, packed_instr, instr))
1350 struct v3d_qpu_instr *instr)
1352 instr->type = V3D_QPU_INSTR_TYPE_BRANCH;
1356 instr->branch.cond = V3D_QPU_BRANCH_COND_ALWAYS;
1359 instr->branch.cond = V3D_QPU_BRANCH_COND_A0 + (cond - 2);
1366 instr->branch.msfign = msfign;
1368 instr->branch.bdi = QPU_GET_FIELD(packed_instr, V3D_QPU_BRANCH_BDI);
1370 instr->branch.ub = packed_instr & V3D_QPU_BRANCH_UB;
1371 if (instr->branch.ub) {
1372 instr->branch.bdu = QPU_GET_FIELD(packed_instr,
1376 instr->branch.raddr_a = QPU_GET_FIELD(packed_instr,
1379 instr->branch.offset = 0;
1381 instr->branch.offset +=
1385 instr->branch.offset +=
1395 struct v3d_qpu_instr *instr)
1398 return v3d_qpu_instr_unpack_alu(devinfo, packed_instr, instr);
1404 instr);
1413 const struct v3d_qpu_instr *instr,
1417 if (!v3d_qpu_sig_pack(devinfo, &instr->sig, &sig))
1421 if (instr->type == V3D_QPU_INSTR_TYPE_ALU) {
1422 *packed_instr |= QPU_SET_FIELD(instr->raddr_a, V3D_QPU_RADDR_A);
1423 *packed_instr |= QPU_SET_FIELD(instr->raddr_b, V3D_QPU_RADDR_B);
1425 if (!v3d_qpu_add_pack(devinfo, instr, packed_instr))
1427 if (!v3d_qpu_mul_pack(devinfo, instr, packed_instr))
1431 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig)) {
1432 if (instr->flags.ac != V3D_QPU_COND_NONE ||
1433 instr->flags.mc != V3D_QPU_COND_NONE ||
1434 instr->flags.apf != V3D_QPU_PF_NONE ||
1435 instr->flags.mpf != V3D_QPU_PF_NONE ||
1436 instr->flags.auf != V3D_QPU_UF_NONE ||
1437 instr->flags.muf != V3D_QPU_UF_NONE) {
1441 flags = instr->sig_addr;
1442 if (instr->sig_magic)
1445 if (!v3d_qpu_flags_pack(devinfo, &instr->flags, &flags))
1451 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig))
1460 const struct v3d_qpu_instr *instr,
1465 if (instr->branch.cond != V3D_QPU_BRANCH_COND_ALWAYS) {
1466 *packed_instr |= QPU_SET_FIELD(2 + (instr->branch.cond -
1471 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,
1474 *packed_instr |= QPU_SET_FIELD(instr->branch.bdi,
1477 if (instr->branch.ub) {
1479 *packed_instr |= QPU_SET_FIELD(instr->branch.bdu,
1483 switch (instr->branch.bdi) {
1486 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,
1489 *packed_instr |= QPU_SET_FIELD((instr->branch.offset &
1493 *packed_instr |= QPU_SET_FIELD(instr->branch.offset >> 24,
1500 if (instr->branch.bdi == V3D_QPU_BRANCH_DEST_REGFILE ||
1501 instr->branch.bdu == V3D_QPU_BRANCH_DEST_REGFILE) {
1502 *packed_instr |= QPU_SET_FIELD(instr->branch.raddr_a,
1511 const struct v3d_qpu_instr *instr,
1516 switch (instr->type) {
1518 return v3d_qpu_instr_pack_alu(devinfo, instr, packed_instr);
1520 return v3d_qpu_instr_pack_branch(devinfo, instr, packed_instr);