Lines Matching refs:mul
651 if (inst->alu.mul.magic_write &&
652 v3d_qpu_magic_waddr_is_tlb(inst->alu.mul.waddr)) {
672 if (inst->alu.mul.magic_write &&
673 v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) {
707 (inst->alu.mul.magic_write &&
708 v3d_qpu_magic_waddr_is_tmu(devinfo, inst->alu.mul.waddr))));
718 (!inst->alu.mul.magic_write ||
719 inst->alu.mul.waddr != V3D_QPU_WADDR_TMUC);
748 if (inst->alu.mul.magic_write &&
749 v3d_qpu_magic_waddr_is_vpm(inst->alu.mul.waddr)) {
771 if (inst->alu.mul.op != V3D_QPU_M_NOP &&
772 inst->alu.mul.magic_write &&
773 inst->alu.mul.waddr == V3D_QPU_WADDR_UNIFA) {
811 if (inst->alu.mul.magic_write && inst->alu.mul.waddr == waddr)
844 if (inst->alu.mul.magic_write &&
845 (inst->alu.mul.waddr == V3D_QPU_WADDR_R4 ||
846 v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr))) {
895 int mul_nsrc = v3d_qpu_mul_op_num_src(inst->alu.mul.op);
899 (mul_nsrc > 0 && inst->alu.mul.a == mux) ||
900 (mul_nsrc > 1 && inst->alu.mul.b == mux));
991 switch (inst->alu.mul.op) {
1017 switch (inst->alu.mul.op) {
1037 if (inst->alu.mul.op != V3D_QPU_M_NOP)