Lines Matching refs:add
92 [V3D_QPU_A_ADD] = "add",
184 [V3D_QPU_M_ADD] = "add",
567 inst->alu.add.op == V3D_QPU_A_TMUWT));
646 if (inst->alu.add.magic_write &&
647 v3d_qpu_magic_waddr_is_tlb(inst->alu.add.waddr)) {
667 if (inst->alu.add.magic_write &&
668 v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) {
685 switch (inst->alu.add.op) {
705 ((inst->alu.add.magic_write &&
706 v3d_qpu_magic_waddr_is_tmu(devinfo, inst->alu.add.waddr)) ||
716 (!inst->alu.add.magic_write ||
717 inst->alu.add.waddr != V3D_QPU_WADDR_TMUC) &&
729 if (v3d_qpu_add_op_reads_vpm(inst->alu.add.op))
740 if (v3d_qpu_add_op_writes_vpm(inst->alu.add.op))
743 if (inst->alu.add.magic_write &&
744 v3d_qpu_magic_waddr_is_vpm(inst->alu.add.waddr)) {
765 if (inst->alu.add.op != V3D_QPU_A_NOP &&
766 inst->alu.add.magic_write &&
767 inst->alu.add.waddr == V3D_QPU_WADDR_UNIFA) {
785 inst->alu.add.op == V3D_QPU_A_VPMWT;
808 if (inst->alu.add.magic_write && inst->alu.add.waddr == waddr)
838 if (inst->alu.add.magic_write &&
839 (inst->alu.add.waddr == V3D_QPU_WADDR_R4 ||
840 v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr))) {
894 int add_nsrc = v3d_qpu_add_op_num_src(inst->alu.add.op);
897 return ((add_nsrc > 0 && inst->alu.add.a == mux) ||
898 (add_nsrc > 1 && inst->alu.add.b == mux) ||
930 switch (inst->alu.add.op) {
967 switch (inst->alu.add.op) {
1008 switch (inst->alu.add.op) {
1035 if (inst->alu.add.op != V3D_QPU_A_NOP)