Lines Matching refs:inst
563 v3d_qpu_waits_on_tmu(const struct v3d_qpu_instr *inst)
565 return (inst->sig.ldtmu ||
566 (inst->type == V3D_QPU_INSTR_TYPE_ALU &&
567 inst->alu.add.op == V3D_QPU_A_TMUWT));
639 v3d_qpu_uses_tlb(const struct v3d_qpu_instr *inst)
641 if (inst->sig.ldtlb ||
642 inst->sig.ldtlbu)
645 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
646 if (inst->alu.add.magic_write &&
647 v3d_qpu_magic_waddr_is_tlb(inst->alu.add.waddr)) {
651 if (inst->alu.mul.magic_write &&
652 v3d_qpu_magic_waddr_is_tlb(inst->alu.mul.waddr)) {
661 v3d_qpu_uses_sfu(const struct v3d_qpu_instr *inst)
663 if (v3d_qpu_instr_is_sfu(inst))
666 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
667 if (inst->alu.add.magic_write &&
668 v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) {
672 if (inst->alu.mul.magic_write &&
673 v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) {
682 v3d_qpu_instr_is_sfu(const struct v3d_qpu_instr *inst)
684 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
685 switch (inst->alu.add.op) {
702 const struct v3d_qpu_instr *inst)
704 return (inst->type == V3D_QPU_INSTR_TYPE_ALU &&
705 ((inst->alu.add.magic_write &&
706 v3d_qpu_magic_waddr_is_tmu(devinfo, inst->alu.add.waddr)) ||
707 (inst->alu.mul.magic_write &&
708 v3d_qpu_magic_waddr_is_tmu(devinfo, inst->alu.mul.waddr))));
713 const struct v3d_qpu_instr *inst)
715 return v3d_qpu_writes_tmu(devinfo, inst) &&
716 (!inst->alu.add.magic_write ||
717 inst->alu.add.waddr != V3D_QPU_WADDR_TMUC) &&
718 (!inst->alu.mul.magic_write ||
719 inst->alu.mul.waddr != V3D_QPU_WADDR_TMUC);
723 v3d_qpu_reads_vpm(const struct v3d_qpu_instr *inst)
725 if (inst->sig.ldvpm)
728 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
729 if (v3d_qpu_add_op_reads_vpm(inst->alu.add.op))
737 v3d_qpu_writes_vpm(const struct v3d_qpu_instr *inst)
739 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
740 if (v3d_qpu_add_op_writes_vpm(inst->alu.add.op))
743 if (inst->alu.add.magic_write &&
744 v3d_qpu_magic_waddr_is_vpm(inst->alu.add.waddr)) {
748 if (inst->alu.mul.magic_write &&
749 v3d_qpu_magic_waddr_is_vpm(inst->alu.mul.waddr)) {
759 const struct v3d_qpu_instr *inst)
764 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
765 if (inst->alu.add.op != V3D_QPU_A_NOP &&
766 inst->alu.add.magic_write &&
767 inst->alu.add.waddr == V3D_QPU_WADDR_UNIFA) {
771 if (inst->alu.mul.op != V3D_QPU_M_NOP &&
772 inst->alu.mul.magic_write &&
773 inst->alu.mul.waddr == V3D_QPU_WADDR_UNIFA) {
782 v3d_qpu_waits_vpm(const struct v3d_qpu_instr *inst)
784 return inst->type == V3D_QPU_INSTR_TYPE_ALU &&
785 inst->alu.add.op == V3D_QPU_A_VPMWT;
789 v3d_qpu_reads_or_writes_vpm(const struct v3d_qpu_instr *inst)
791 return v3d_qpu_reads_vpm(inst) || v3d_qpu_writes_vpm(inst);
795 v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst)
797 return v3d_qpu_reads_vpm(inst) ||
798 v3d_qpu_writes_vpm(inst) ||
799 v3d_qpu_waits_vpm(inst);
804 const struct v3d_qpu_instr *inst,
807 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
808 if (inst->alu.add.magic_write && inst->alu.add.waddr == waddr)
811 if (inst->alu.mul.magic_write && inst->alu.mul.waddr == waddr)
815 if (v3d_qpu_sig_writes_address(devinfo, &inst->sig) &&
816 inst->sig_magic && inst->sig_addr == waddr) {
825 const struct v3d_qpu_instr *inst)
827 if (qpu_writes_magic_waddr_explicitly(devinfo, inst, V3D_QPU_WADDR_R3))
830 return (devinfo->ver < 41 && inst->sig.ldvary) || inst->sig.ldvpm;
835 const struct v3d_qpu_instr *inst)
837 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
838 if (inst->alu.add.magic_write &&
839 (inst->alu.add.waddr == V3D_QPU_WADDR_R4 ||
840 v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr))) {
844 if (inst->alu.mul.magic_write &&
845 (inst->alu.mul.waddr == V3D_QPU_WADDR_R4 ||
846 v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr))) {
851 if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) {
852 if (inst->sig_magic && inst->sig_addr == V3D_QPU_WADDR_R4)
854 } else if (inst->sig.ldtmu) {
863 const struct v3d_qpu_instr *inst)
865 if (qpu_writes_magic_waddr_explicitly(devinfo, inst, V3D_QPU_WADDR_R5))
868 return inst->sig.ldvary || inst->sig.ldunif || inst->sig.ldunifa;
873 const struct v3d_qpu_instr *inst)
875 if (v3d_qpu_writes_r5(devinfo, inst))
877 if (v3d_qpu_writes_r4(devinfo, inst))
879 if (v3d_qpu_writes_r3(devinfo, inst))
881 if (qpu_writes_magic_waddr_explicitly(devinfo, inst, V3D_QPU_WADDR_R2))
883 if (qpu_writes_magic_waddr_explicitly(devinfo, inst, V3D_QPU_WADDR_R1))
885 if (qpu_writes_magic_waddr_explicitly(devinfo, inst, V3D_QPU_WADDR_R0))
892 v3d_qpu_uses_mux(const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux)
894 int add_nsrc = v3d_qpu_add_op_num_src(inst->alu.add.op);
895 int mul_nsrc = v3d_qpu_mul_op_num_src(inst->alu.mul.op);
897 return ((add_nsrc > 0 && inst->alu.add.a == mux) ||
898 (add_nsrc > 1 && inst->alu.add.b == mux) ||
899 (mul_nsrc > 0 && inst->alu.mul.a == mux) ||
900 (mul_nsrc > 1 && inst->alu.mul.b == mux));
919 v3d_qpu_reads_flags(const struct v3d_qpu_instr *inst)
921 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
922 return inst->branch.cond != V3D_QPU_BRANCH_COND_ALWAYS;
923 } else if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
924 if (inst->flags.ac != V3D_QPU_COND_NONE ||
925 inst->flags.mc != V3D_QPU_COND_NONE ||
926 inst->flags.auf != V3D_QPU_UF_NONE ||
927 inst->flags.muf != V3D_QPU_UF_NONE)
930 switch (inst->alu.add.op) {
949 v3d_qpu_writes_flags(const struct v3d_qpu_instr *inst)
951 if (inst->flags.apf != V3D_QPU_PF_NONE ||
952 inst->flags.mpf != V3D_QPU_PF_NONE ||
953 inst->flags.auf != V3D_QPU_UF_NONE ||
954 inst->flags.muf != V3D_QPU_UF_NONE) {
962 v3d_qpu_unpacks_f32(const struct v3d_qpu_instr *inst)
964 if (inst->type != V3D_QPU_INSTR_TYPE_ALU)
967 switch (inst->alu.add.op) {
991 switch (inst->alu.mul.op) {
1003 v3d_qpu_unpacks_f16(const struct v3d_qpu_instr *inst)
1005 if (inst->type != V3D_QPU_INSTR_TYPE_ALU)
1008 switch (inst->alu.add.op) {
1017 switch (inst->alu.mul.op) {
1029 v3d_qpu_is_nop(struct v3d_qpu_instr *inst)
1033 if (inst->type != V3D_QPU_INSTR_TYPE_ALU)
1035 if (inst->alu.add.op != V3D_QPU_A_NOP)
1037 if (inst->alu.mul.op != V3D_QPU_M_NOP)
1039 if (memcmp(&inst->sig, &nosig, sizeof(nosig)))