Lines Matching refs:instr
60 const struct v3d_qpu_instr *instr, uint8_t mux)
63 append(disasm, "rf%d", instr->raddr_a);
65 if (instr->sig.small_imm) {
69 instr->raddr_b,
78 append(disasm, "rf%d", instr->raddr_b);
102 const struct v3d_qpu_instr *instr)
104 bool has_dst = v3d_qpu_add_op_has_dst(instr->alu.add.op);
105 int num_src = v3d_qpu_add_op_num_src(instr->alu.add.op);
107 append(disasm, "%s", v3d_qpu_add_op_name(instr->alu.add.op));
108 if (!v3d_qpu_sig_writes_address(disasm->devinfo, &instr->sig))
109 append(disasm, "%s", v3d_qpu_cond_name(instr->flags.ac));
110 append(disasm, "%s", v3d_qpu_pf_name(instr->flags.apf));
111 append(disasm, "%s", v3d_qpu_uf_name(instr->flags.auf));
116 v3d_qpu_disasm_waddr(disasm, instr->alu.add.waddr,
117 instr->alu.add.magic_write);
118 append(disasm, v3d_qpu_pack_name(instr->alu.add.output_pack));
124 v3d_qpu_disasm_raddr(disasm, instr, instr->alu.add.a);
126 v3d_qpu_unpack_name(instr->alu.add.a_unpack));
131 v3d_qpu_disasm_raddr(disasm, instr, instr->alu.add.b);
133 v3d_qpu_unpack_name(instr->alu.add.b_unpack));
139 const struct v3d_qpu_instr *instr)
141 bool has_dst = v3d_qpu_mul_op_has_dst(instr->alu.mul.op);
142 int num_src = v3d_qpu_mul_op_num_src(instr->alu.mul.op);
147 append(disasm, "%s", v3d_qpu_mul_op_name(instr->alu.mul.op));
148 if (!v3d_qpu_sig_writes_address(disasm->devinfo, &instr->sig))
149 append(disasm, "%s", v3d_qpu_cond_name(instr->flags.mc));
150 append(disasm, "%s", v3d_qpu_pf_name(instr->flags.mpf));
151 append(disasm, "%s", v3d_qpu_uf_name(instr->flags.muf));
153 if (instr->alu.mul.op == V3D_QPU_M_NOP)
159 v3d_qpu_disasm_waddr(disasm, instr->alu.mul.waddr,
160 instr->alu.mul.magic_write);
161 append(disasm, v3d_qpu_pack_name(instr->alu.mul.output_pack));
167 v3d_qpu_disasm_raddr(disasm, instr, instr->alu.mul.a);
169 v3d_qpu_unpack_name(instr->alu.mul.a_unpack));
174 v3d_qpu_disasm_raddr(disasm, instr, instr->alu.mul.b);
176 v3d_qpu_unpack_name(instr->alu.mul.b_unpack));
182 const struct v3d_qpu_instr *instr)
187 if (!instr->sig_magic)
188 append(disasm, ".rf%d", instr->sig_addr);
192 instr->sig_addr);
196 append(disasm, ".UNKNOWN%d", instr->sig_addr);
202 const struct v3d_qpu_instr *instr)
204 const struct v3d_qpu_sig *sig = &instr->sig;
226 v3d_qpu_disasm_sig_addr(disasm, instr);
232 v3d_qpu_disasm_sig_addr(disasm, instr);
236 v3d_qpu_disasm_sig_addr(disasm, instr);
240 v3d_qpu_disasm_sig_addr(disasm, instr);
246 v3d_qpu_disasm_sig_addr(disasm, instr);
252 v3d_qpu_disasm_sig_addr(disasm, instr);
260 const struct v3d_qpu_instr *instr)
262 v3d_qpu_disasm_add(disasm, instr);
263 v3d_qpu_disasm_mul(disasm, instr);
264 v3d_qpu_disasm_sig(disasm, instr);
269 const struct v3d_qpu_instr *instr)
272 if (instr->branch.ub)
274 append(disasm, "%s", v3d_qpu_branch_cond_name(instr->branch.cond));
275 append(disasm, "%s", v3d_qpu_msfign_name(instr->branch.msfign));
277 switch (instr->branch.bdi) {
279 append(disasm, " zero_addr+0x%08x", instr->branch.offset);
283 append(disasm, " %d", instr->branch.offset);
291 append(disasm, " rf%d", instr->branch.raddr_a);
295 if (instr->branch.ub) {
296 switch (instr->branch.bdu) {
310 append(disasm, ", rf%d", instr->branch.raddr_a);
318 const struct v3d_qpu_instr *instr)
326 switch (instr->type) {
328 v3d_qpu_disasm_alu(&disasm, instr);
332 v3d_qpu_disasm_branch(&disasm, instr);
347 struct v3d_qpu_instr instr;
348 bool ok = v3d_qpu_instr_unpack(devinfo, inst, &instr);
351 return v3d_qpu_decode(devinfo, &instr);
356 const struct v3d_qpu_instr *instr)
358 const char *decoded = v3d_qpu_decode(devinfo, instr);