Lines Matching refs:qpu
25 #include "qpu/qpu_instr.h"
26 #include "qpu/qpu_disasm.h"
137 if (qinst->qpu.type != V3D_QPU_INSTR_TYPE_ALU ||
138 qinst->qpu.alu.mul.op != V3D_QPU_M_MOV ||
139 qinst->qpu.alu.add.op != V3D_QPU_A_NOP ||
140 memcmp(&qinst->qpu.sig, &no_sig, sizeof(no_sig)) != 0) {
145 enum v3d_qpu_waddr waddr = qinst->qpu.alu.mul.waddr;
146 if (qinst->qpu.alu.mul.magic_write) {
150 if (qinst->qpu.alu.mul.a !=
157 switch (qinst->qpu.alu.mul.a) {
159 raddr = qinst->qpu.raddr_a;
162 raddr = qinst->qpu.raddr_b;
174 if (qinst->qpu.alu.mul.a_unpack != V3D_QPU_UNPACK_NONE ||
175 qinst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE ||
176 qinst->qpu.flags.mc != V3D_QPU_COND_NONE ||
177 qinst->qpu.flags.mpf != V3D_QPU_PF_NONE ||
178 qinst->qpu.flags.muf != V3D_QPU_UF_NONE) {
194 fprintf(stderr, "translating qinst to qpu: ");
238 temp->qpu.sig.ldvpm = true;
273 if (qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU) {
274 if (qinst->qpu.sig.ldunif || qinst->qpu.sig.ldunifa) {
275 assert(qinst->qpu.alu.add.op == V3D_QPU_A_NOP);
276 assert(qinst->qpu.alu.mul.op == V3D_QPU_M_NOP);
282 if (qinst->qpu.sig.ldunif) {
283 qinst->qpu.sig.ldunif = false;
284 qinst->qpu.sig.ldunifrf = true;
286 qinst->qpu.sig.ldunifa = false;
287 qinst->qpu.sig.ldunifarf = true;
289 qinst->qpu.sig_addr = dst.index;
290 qinst->qpu.sig_magic = dst.magic;
293 &qinst->qpu.sig)) {
294 assert(qinst->qpu.alu.add.op == V3D_QPU_A_NOP);
295 assert(qinst->qpu.alu.mul.op == V3D_QPU_M_NOP);
297 qinst->qpu.sig_addr = dst.index;
298 qinst->qpu.sig_magic = dst.magic;
299 } else if (qinst->qpu.alu.add.op != V3D_QPU_A_NOP) {
300 assert(qinst->qpu.alu.mul.op == V3D_QPU_M_NOP);
302 set_src(&qinst->qpu,
303 &qinst->qpu.alu.add.a, src[0]);
306 set_src(&qinst->qpu,
307 &qinst->qpu.alu.add.b, src[1]);
310 qinst->qpu.alu.add.waddr = dst.index;
311 qinst->qpu.alu.add.magic_write = dst.magic;
314 set_src(&qinst->qpu,
315 &qinst->qpu.alu.mul.a, src[0]);
318 set_src(&qinst->qpu,
319 &qinst->qpu.alu.mul.b, src[1]);
322 qinst->qpu.alu.mul.waddr = dst.index;
323 qinst->qpu.alu.mul.magic_write = dst.magic;
331 assert(qinst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH);
339 struct v3d_qpu_instr qpu;
340 ASSERTED bool ok = v3d_qpu_instr_unpack(devinfo, instruction, &qpu);
343 if (qpu.sig.ldunif ||
344 qpu.sig.ldunifrf ||
345 qpu.sig.ldtlbu ||
346 qpu.sig.wrtmuc) {
350 if (qpu.type == V3D_QPU_INSTR_TYPE_BRANCH)
353 if (qpu.type == V3D_QPU_INSTR_TYPE_ALU) {
354 if (qpu.alu.add.magic_write &&
355 v3d_qpu_magic_waddr_loads_unif(qpu.alu.add.waddr)) {
359 if (qpu.alu.mul.magic_write &&
360 v3d_qpu_magic_waddr_loads_unif(qpu.alu.mul.waddr)) {
418 bool ok = v3d_qpu_instr_pack(c->devinfo, &inst->qpu,
428 if (v3d_qpu_is_nop(&inst->qpu))