Lines Matching defs:src
90 * Allocates the src register (accumulator or register file) into the RADDR
94 set_src(struct v3d_qpu_instr *instr, enum v3d_qpu_mux *mux, struct qpu_reg src)
96 if (src.smimm) {
102 if (src.magic) {
103 assert(src.index >= V3D_QPU_WADDR_R0 &&
104 src.index <= V3D_QPU_WADDR_R5);
105 *mux = src.index - V3D_QPU_WADDR_R0 + V3D_QPU_MUX_R0;
113 instr->raddr_a = src.index;
116 if (instr->raddr_a == src.index) {
123 src.index == instr->raddr_b);
125 instr->raddr_b = src.index;
205 struct qpu_reg src[ARRAY_SIZE(qinst->src)];
207 int index = qinst->src[i].index;
208 switch (qinst->src[i].file) {
210 src[i] = qpu_reg(qinst->src[i].index);
213 src[i] = qpu_magic(qinst->src[i].index);
219 src[i] = qpu_reg(0);
225 src[i] = temp_registers[index];
228 src[i].smimm = true;
232 assert((int)qinst->src[i].index >=
235 last_vpm_read_index = qinst->src[i].index;
240 src[i] = qpu_magic(V3D_QPU_WADDR_R3);
303 &qinst->qpu.alu.add.a, src[0]);
307 &qinst->qpu.alu.add.b, src[1]);
315 &qinst->qpu.alu.mul.a, src[0]);
319 &qinst->qpu.alu.mul.b, src[1]);