Lines Matching refs:tmu_writes
46 uint32_t *tmu_writes)
48 if (tmu_writes)
49 (*tmu_writes)++;
71 * If 'tmu_writes' is not NULL, then it just counts required register writes,
89 unsigned *tmu_writes)
94 assert(tmu_writes || (s_out && p2_unpacked));
101 if (tmu_writes)
102 (*tmu_writes)++;
110 tmu_writes);
117 tmu_writes);
125 tmu_writes);
131 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUB, src, tmu_writes);
137 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUB, src, tmu_writes);
138 if (!tmu_writes) {
155 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUDREF, src, tmu_writes);
162 if (!tmu_writes) {
177 if (!tmu_writes) {
188 (*tmu_writes)++;
204 unsigned *tmu_writes)
212 p2_unpacked, s, tmu_writes);
219 unsigned tmu_writes = 0;
220 vir_tex_handle_srcs(c, instr, NULL, NULL, &tmu_writes);
221 return tmu_writes;
252 const unsigned tmu_writes = get_required_tex_tmu_writes(c, instr);
257 while (tmu_writes > 16 / c->threads)
419 * If 'tmu_writes' is not NULL, then it just counts required register writes,
434 uint32_t *tmu_writes)
436 if (tmu_writes)
437 *tmu_writes = 0;
450 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUT, src, tmu_writes);
456 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUT, src_1_1, tmu_writes);
457 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUR, src_1_2, tmu_writes);
470 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUI, src, tmu_writes);
479 tmu_writes);
486 tmu_writes);
491 if (!tmu_writes && vir_in_nonuniform_control_flow(c) &&
497 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUSF, src_1_0, tmu_writes);
499 if (!tmu_writes && vir_in_nonuniform_control_flow(c) &&
512 unsigned tmu_writes;
514 &tmu_writes);
515 return tmu_writes;
581 const uint32_t tmu_writes =
587 while (tmu_writes > 16 / c->threads)