Lines Matching refs:src

97         switch (instr->src[src_idx].src_type) {
100 s = ntq_get_src(c, instr->src[src_idx].src, 0);
107 struct qreg src =
108 ntq_get_src(c, instr->src[src_idx].src, 1);
109 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUT, src,
114 struct qreg src =
115 ntq_get_src(c, instr->src[src_idx].src, 2);
116 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUR, src,
121 struct qreg src =
122 ntq_get_src(c, instr->src[src_idx].src,
124 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUI, src,
130 struct qreg src = ntq_get_src(c, instr->src[src_idx].src, 0);
131 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUB, src, tmu_writes);
136 struct qreg src = ntq_get_src(c, instr->src[src_idx].src, 0);
137 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUB, src, tmu_writes);
154 struct qreg src = ntq_get_src(c, instr->src[src_idx].src, 0);
155 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUDREF, src, tmu_writes);
160 bool is_const_offset = nir_src_is_const(instr->src[src_idx].src);
164 nir_src_comp_as_int(instr->src[src_idx].src, 0);
167 nir_src_comp_as_int(instr->src[src_idx].src, 1);
170 nir_src_comp_as_int(instr->src[src_idx].src, 2);
174 ntq_get_src(c, instr->src[src_idx].src, 0);
176 ntq_get_src(c, instr->src[src_idx].src, 1);
449 struct qreg src = ntq_get_src(c, instr->src[1], 1);
450 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUT, src, tmu_writes);
454 struct qreg src_1_1 = ntq_get_src(c, instr->src[1], 1);
455 struct qreg src_1_2 = ntq_get_src(c, instr->src[1], 2);
469 struct qreg src = ntq_get_src(c, instr->src[1], is_1d ? 1 : 2);
470 vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUI, src, tmu_writes);
477 struct qreg src_3_i = ntq_get_src(c, instr->src[3], i);
484 struct qreg src_4_0 = ntq_get_src(c, instr->src[4], 0);
490 struct qreg src_1_0 = ntq_get_src(c, instr->src[1], 0);
523 unsigned unit = nir_src_as_uint(instr->src[0]);