Lines Matching refs:waddr
140 (inst->alu.add.waddr == V3D_QPU_WADDR_TLB ||
141 inst->alu.add.waddr == V3D_QPU_WADDR_TLBU))
145 (inst->alu.mul.waddr == V3D_QPU_WADDR_TLB ||
146 inst->alu.mul.waddr == V3D_QPU_WADDR_TLBU))
173 tmu_write_is_sequence_terminator(uint32_t waddr)
175 switch (waddr) {
189 can_reorder_tmu_write(const struct v3d_device_info *devinfo, uint32_t waddr)
194 if (tmu_write_is_sequence_terminator(waddr))
197 if (waddr == V3D_QPU_WADDR_TMUD)
205 uint32_t waddr, bool magic)
208 add_write_dep(state, &state->last_rf[waddr], n);
209 } else if (v3d_qpu_magic_waddr_is_tmu(state->devinfo, waddr)) {
210 if (can_reorder_tmu_write(state->devinfo, waddr))
215 if (tmu_write_is_sequence_terminator(waddr))
217 } else if (v3d_qpu_magic_waddr_is_sfu(waddr)) {
220 switch (waddr) {
225 &state->last_r[waddr - V3D_QPU_WADDR_R0],
264 fprintf(stderr, "Unknown waddr %d\n", waddr);
369 process_waddr_deps(state, n, inst->alu.add.waddr,
373 process_waddr_deps(state, n, inst->alu.mul.waddr,
604 uint32_t waddr) {
610 inst->raddr_a == waddr)
614 !inst->sig.small_imm && (inst->raddr_b == waddr))
722 v3d_qpu_magic_waddr_is_tsy(inst->alu.add.waddr)) {
1278 enum v3d_qpu_waddr waddr,
1281 if (v3d_qpu_magic_waddr_is_sfu(waddr))
1283 else if (devinfo->ver >= 40 && waddr == V3D_QPU_WADDR_UNIFA)
1292 scoreboard->last_stallable_sfu_reg = inst->alu.add.waddr;
1310 inst->alu.add.waddr,
1324 inst->alu.mul.waddr,
1357 enum v3d_qpu_waddr waddr,
1383 if (v3d_qpu_magic_waddr_is_tmu(devinfo, waddr) &&
1389 if (v3d_qpu_magic_waddr_is_sfu(waddr))
1410 before_inst->alu.add.waddr,
1417 before_inst->alu.mul.waddr,
1592 (v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.add.waddr) ||
1593 v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.mul.waddr))) {
2108 prev->qpu.alu.add.waddr == ldvary_index) {
2115 prev->qpu.alu.mul.waddr == ldvary_index) {