Lines Matching refs:result
62 * cycles between this instruction being scheduled and when its result
629 /* We define a max schedule priority to allow negative priorities as result of
698 uint32_t result = 0;
700 result |= V3D_PERIPHERAL_VPM_READ;
702 result |= V3D_PERIPHERAL_VPM_WRITE;
704 result |= V3D_PERIPHERAL_VPM_WAIT;
707 result |= V3D_PERIPHERAL_TMU_WRITE;
709 result |= V3D_PERIPHERAL_TMU_READ;
711 result |= V3D_PERIPHERAL_TMU_WRTMUC_SIG;
714 result |= V3D_PERIPHERAL_SFU;
717 result |= V3D_PERIPHERAL_TLB;
723 result |= V3D_PERIPHERAL_TSY;
727 result |= V3D_PERIPHERAL_TMU_WAIT;
730 return result;
805 qpu_merge_raddrs(struct v3d_qpu_instr *result,
823 result->sig.small_imm = true;
824 result->raddr_b = add_instr->sig.small_imm ?
833 result->raddr_a = raddr_a;
835 if (!result->sig.small_imm) {
839 result->alu.add.a = V3D_QPU_MUX_A;
842 result->alu.add.b = V3D_QPU_MUX_A;
848 result->alu.mul.a = V3D_QPU_MUX_A;
851 result->alu.mul.b = V3D_QPU_MUX_A;
859 result->raddr_b = raddr_b;
863 result->alu.add.a = V3D_QPU_MUX_B;
866 result->alu.add.b = V3D_QPU_MUX_B;
872 result->alu.mul.a = V3D_QPU_MUX_B;
875 result->alu.mul.b = V3D_QPU_MUX_B;
935 struct v3d_qpu_instr *result,
1040 *result = merge;
1042 assert(ok || (a != result && b != result));
1388 /* Assume that anything depending on us is consuming the SFU result. */
1586 /* No scheduling SFU when the result would land in the other
2231 fprintf(stderr, " result: ");