Lines Matching defs:after
68 /* When walking the instructions in reverse, we need to swap before/after in
96 struct schedule_node *after,
102 if (!before || !after)
105 assert(before != after);
108 dag_add_edge(&before->dag, &after->dag, edge_data);
110 dag_add_edge(&after->dag, &before->dag, edge_data);
116 struct schedule_node *after)
118 add_dep(state, before, after, false);
124 struct schedule_node *after)
126 add_dep(state, *before, after, true);
127 *before = after;
392 /* All accumulator contents and flags are undefined after the
400 /* Scoreboard-locking operations have to stay after the last
413 /* Keep TMU loads after their TMU lookup terminator */
431 * all writes after all reads.
568 /* Don't schedule any other r4 write too soon after an SFU write.
1088 * left. We'll move it up to fit its delay slots after we
1149 /* No branch with cond != 0,2,3 and msfign != 0 after
1358 const struct v3d_qpu_instr *after)
1384 v3d_qpu_waits_on_tmu(after)) {
1397 struct schedule_node *before, struct schedule_node *after)
1400 const struct v3d_qpu_instr *after_inst = &after->inst->qpu;
1577 * delay slots. Because the actual execution of the thrsw happens after the
1604 * be after the 2 delay slots following the thrsw instruction.
1606 * right after unifa:
1621 * This is called for instructions scheduled *after* a thrsw signal that may
1623 * scheduled after the thrsw, we need to be careful when placing them into
1636 * manually, so any instructions scheduled after a thrsw shold be
1646 * also apply to instructions scheduled after the thrsw that we want
1667 * So avoid placing TMU instructions scheduled after the thrsw into
1672 * after the thrsw into the sequence before the thrsw.
1706 * therefore, if we have a TSY sync right after a thread switch, we
1910 /* Can't place a branch with msfign != 0 and cond != 0,2,3 after
1989 * first instructions in the successor block after scheduling
2356 * block must follow immediately after this one.
2393 * successor was scheduled just after the