Lines Matching refs:instr
176 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src)
178 if (nir_src_is_const(instr->src[src])) {
179 int64_t add_val = nir_src_as_int(instr->src[src]);
190 v3d_general_tmu_op(nir_intrinsic_instr *instr)
192 switch (instr->intrinsic) {
205 return v3d_get_op_for_atomic_add(instr, 2);
208 return v3d_get_op_for_atomic_add(instr, 1);
353 nir_intrinsic_instr *instr,
373 last_component < instr->num_components);
376 struct qreg data = ntq_get_src(c, instr->src[0], i);
387 *type_size = nir_src_bit_size(instr->src[0]) / 8;
411 nir_intrinsic_instr *instr,
418 struct qreg data = ntq_get_src(c, instr->src[1 + has_index], 0);
425 data = ntq_get_src(c, instr->src[2 + has_index], 0);
445 nir_intrinsic_instr *instr,
456 ntq_get_src(c, instr->src[offset_src], 0);
478 struct qreg data = ntq_get_src(c, instr->src[offset_src], 0);
503 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
506 uint32_t tmu_op = v3d_general_tmu_op(instr);
513 ((instr->intrinsic == nir_intrinsic_ssbo_atomic_add ||
514 instr->intrinsic == nir_intrinsic_shared_atomic_add ||
515 instr->intrinsic == nir_intrinsic_global_atomic_add_2x32) &&
519 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
520 instr->intrinsic == nir_intrinsic_store_scratch ||
521 instr->intrinsic == nir_intrinsic_store_shared ||
522 instr->intrinsic == nir_intrinsic_store_global_2x32);
524 bool is_load = (instr->intrinsic == nir_intrinsic_load_uniform ||
525 instr->intrinsic == nir_intrinsic_load_ubo ||
526 instr->intrinsic == nir_intrinsic_load_ssbo ||
527 instr->intrinsic == nir_intrinsic_load_scratch ||
528 instr->intrinsic == nir_intrinsic_load_shared ||
529 instr->intrinsic == nir_intrinsic_load_global_2x32);
540 if (instr->intrinsic == nir_intrinsic_load_uniform) {
542 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
543 instr->intrinsic == nir_intrinsic_load_ubo ||
544 instr->intrinsic == nir_intrinsic_load_scratch ||
545 instr->intrinsic == nir_intrinsic_load_shared ||
546 instr->intrinsic == nir_intrinsic_load_global_2x32 ||
555 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
558 const_offset = nir_src_as_uint(instr->src[offset_src]);
561 if (instr->intrinsic == nir_intrinsic_load_uniform) {
562 const_offset += nir_intrinsic_base(instr);
566 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
567 uint32_t index = nir_src_as_uint(instr->src[0]);
583 if (instr->intrinsic == nir_intrinsic_load_scratch ||
584 instr->intrinsic == nir_intrinsic_store_scratch) {
588 const_offset += nir_intrinsic_base(instr);
598 nir_src_as_uint(instr->src[is_store ?
612 const uint32_t dest_components = nir_intrinsic_dest_components(instr);
614 uint32_t writemask = is_store ? nir_intrinsic_write_mask(instr) : 0;
622 emit_tmu_general_store_writes(c, mode, instr,
629 emit_tmu_general_atomic_writes(c, mode, instr,
633 type_size = nir_dest_bit_size(instr->dest) / 8;
645 num_components = instr->num_components;
683 emit_tmu_general_address_write(c, mode, instr, config,
709 ntq_add_pending_tmu_flush(c, &instr->dest,
876 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
879 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
880 unsigned chan = ffs(instr->dest.write_mask) - 1;
881 struct qreg r = ntq_get_src(c, instr->src[src].src,
882 instr->src[src].swizzle[chan]);
884 assert(!instr->src[src].abs);
885 assert(!instr->src[src].negate);
897 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
899 unsigned unit = instr->texture_index;
900 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
901 int dest_size = nir_tex_instr_dest_size(instr);
905 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
911 if (instr->is_array && i == dest_size - 1)
918 switch (instr->sampler_dim) {
926 if (!(instr->is_array && i == dest_size - 1)) {
939 ntq_store_dest(c, &instr->dest, i, size);
944 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
946 unsigned unit = instr->texture_index;
952 switch (instr->op) {
954 ntq_store_dest(c, &instr->dest, 0,
958 ntq_store_dest(c, &instr->dest, 0,
962 ntq_emit_txs(c, instr);
969 v3d40_vir_emit_tex(c, instr);
971 v3d33_vir_emit_tex(c, instr);
1239 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
1240 if (!instr)
1243 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
1244 * moving emission of the ALU instr down past another write of the
1247 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1248 if (!instr->src[i].src.is_ssa)
1252 return instr;
1423 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
1426 assert(!instr->dest.saturate);
1432 if (instr->op == nir_op_vec2 ||
1433 instr->op == nir_op_vec3 ||
1434 instr->op == nir_op_vec4) {
1436 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1437 srcs[i] = ntq_get_src(c, instr->src[i].src,
1438 instr->src[i].swizzle[0]);
1439 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1440 ntq_store_dest(c, &instr->dest.dest, i,
1446 struct qreg src[nir_op_infos[instr->op].num_inputs];
1447 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1448 src[i] = ntq_get_alu_src(c, instr, i);
1453 switch (instr->op) {
1482 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
1509 assert(nir_src_bit_size(instr->src[0].src) == 32);
1515 assert(nir_src_bit_size(instr->src[0].src) == 32);
1520 assert(nir_src_bit_size(instr->src[0].src) == 16);
1526 uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
1543 uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
1561 assert(nir_src_bit_size(instr->src[0].src) == 32 ||
1562 nir_src_bit_size(instr->src[0].src) == 16);
1571 uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
1584 uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
1648 ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
1671 ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
1680 ntq_emit_bool_to_cond(c, instr->src[0].src),
1799 nir_print_instr(&instr->instr, stderr);
1807 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1808 ntq_store_dest(c, &instr->dest.dest,
1809 ffs(instr->dest.write_mask) - 1, result);
2511 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
2517 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
2518 for (int i = 0; i < instr->def.num_components; i++)
2519 qregs[i] = vir_uniform_ui(c, instr->value[i].u32);
2521 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
2525 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
2527 unsigned image_index = nir_src_as_uint(instr->src[0]);
2528 bool is_array = nir_intrinsic_image_array(instr);
2530 assert(nir_src_as_uint(instr->src[1]) == 0);
2532 ntq_store_dest(c, &instr->dest, 0,
2534 if (instr->num_components > 1) {
2535 ntq_store_dest(c, &instr->dest, 1,
2537 instr->num_components == 2 && is_array ?
2542 if (instr->num_components > 2) {
2543 ntq_store_dest(c, &instr->dest, 2,
2553 vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr)
2557 int rt = nir_src_as_uint(instr->src[0]);
2560 int sample_index = nir_intrinsic_base(instr) ;
2563 int component = nir_intrinsic_component(instr);
2681 ntq_store_dest(c, &instr->dest, 0,
2686 ntq_emit_load_unifa(struct v3d_compile *c, nir_intrinsic_instr *instr);
2723 ntq_emit_load_uniform(struct v3d_compile *c, nir_intrinsic_instr *instr)
2726 assert(nir_dest_bit_size(instr->dest) == 32 ||
2727 instr->num_components == 1);
2730 if (nir_src_is_const(instr->src[0])) {
2731 int offset = (nir_intrinsic_base(instr) +
2732 nir_src_as_uint(instr->src[0]));
2734 if (try_emit_uniform(c, offset, instr->num_components,
2735 &instr->dest, QUNIFORM_UNIFORM)) {
2740 if (!ntq_emit_load_unifa(c, instr)) {
2741 ntq_emit_tmu_general(c, instr, false, false);
2747 ntq_emit_inline_ubo_load(struct v3d_compile *c, nir_intrinsic_instr *instr)
2757 uint32_t index = nir_src_as_uint(instr->src[0]);
2762 assert(nir_dest_bit_size(instr->dest) == 32 ||
2763 instr->num_components == 1);
2765 if (nir_src_is_const(instr->src[1])) {
2769 int offset = nir_src_as_uint(instr->src[1]);
2770 if (try_emit_uniform(c, offset, instr->num_components,
2771 &instr->dest,
2782 ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
2796 nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0]);
2822 index += nir_intrinsic_component(instr);
2823 for (int i = 0; i < instr->num_components; i++) {
2825 ntq_store_dest(c, &instr->dest, i,
2829 for (int i = 0; i < instr->num_components; i++) {
2830 int comp = nir_intrinsic_component(instr) + i;
2832 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, input));
2845 nir_intrinsic_instr *instr)
2847 assert(instr->intrinsic == nir_intrinsic_store_tlb_sample_color_v3d);
2849 unsigned rt = nir_src_as_uint(instr->src[1]);
2852 unsigned sample_idx = nir_intrinsic_base(instr);
2856 for (int i = 0; i < instr->num_components; i++) {
2858 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
2864 nir_intrinsic_instr *instr)
2866 unsigned offset = (nir_intrinsic_base(instr) +
2867 nir_src_as_uint(instr->src[1])) * 4 +
2868 nir_intrinsic_component(instr);
2869 for (int i = 0; i < instr->num_components; i++) {
2871 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
2876 emit_store_output_gs(struct v3d_compile *c, nir_intrinsic_instr *instr)
2878 assert(instr->num_components == 1);
2880 struct qreg offset = ntq_get_src(c, instr->src[1], 0);
2882 uint32_t base_offset = nir_intrinsic_base(instr);
2896 struct qreg val = ntq_get_src(c, instr->src[0], 0);
2906 !nir_src_is_divergent(instr->src[1]);
2917 emit_store_output_vs(struct v3d_compile *c, nir_intrinsic_instr *instr)
2920 assert(instr->num_components == 1);
2922 uint32_t base = nir_intrinsic_base(instr);
2923 struct qreg val = ntq_get_src(c, instr->src[0], 0);
2925 if (nir_src_is_const(instr->src[1])) {
2927 base + nir_src_as_uint(instr->src[1]));
2930 ntq_get_src(c, instr->src[1], 1),
2934 !nir_src_is_divergent(instr->src[1]);
2940 ntq_emit_store_output(struct v3d_compile *c, nir_intrinsic_instr *instr)
2943 ntq_emit_color_write(c, instr);
2945 emit_store_output_gs(c, instr);
2947 emit_store_output_vs(c, instr);
3102 ntq_emit_load_unifa(struct v3d_compile *c, nir_intrinsic_instr *instr)
3104 assert(instr->intrinsic == nir_intrinsic_load_ubo ||
3105 instr->intrinsic == nir_intrinsic_load_ssbo ||
3106 instr->intrinsic == nir_intrinsic_load_uniform);
3108 bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
3109 bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
3110 bool is_ssbo = instr->intrinsic == nir_intrinsic_load_ssbo;
3119 nir_src offset = is_uniform ? instr->src[0] : instr->src[1];
3127 if (is_ssbo && !(nir_intrinsic_access(instr) & ACCESS_NON_WRITEABLE))
3139 const_offset += nir_intrinsic_base(instr);
3147 uint32_t bit_size = nir_dest_bit_size(instr->dest);
3168 uint32_t index = is_uniform ? 0 : nir_src_as_uint(instr->src[0]);
3223 uint32_t num_components = nir_intrinsic_dest_components(instr);
3230 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, data));
3259 ntq_store_dest(c, &instr->dest, i,
3312 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
3314 switch (instr->intrinsic) {
3316 ntq_emit_load_uniform(c, instr);
3320 ntq_emit_tmu_general(c, instr, false, true);
3325 if (ntq_emit_inline_ubo_load(c, instr))
3329 if (!ntq_emit_load_unifa(c, instr)) {
3330 ntq_emit_tmu_general(c, instr, false, false);
3346 ntq_emit_tmu_general(c, instr, false, false);
3360 ntq_emit_tmu_general(c, instr, false, true);
3375 ntq_emit_tmu_general(c, instr, true, false);
3380 ntq_emit_tmu_general(c, instr, true, false);
3395 v3d40_vir_emit_image_load_store(c, instr);
3399 v3d40_vir_emit_image_load_store(c, instr);
3408 ntq_store_dest(c, &instr->dest, 0,
3410 nir_src_comp_as_uint(instr->src[0], 0)));
3414 ntq_store_dest(c, &instr->dest, 0,
3416 nir_src_comp_as_uint(instr->src[0], 0)));
3420 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) {
3421 ntq_store_dest(c, &instr->dest, i,
3423 nir_intrinsic_ucp_id(instr) *
3429 ntq_store_dest(c, &instr->dest, 0,
3434 ntq_store_dest(c, &instr->dest, 0,
3439 ntq_store_dest(c, &instr->dest, 0,
3444 ntq_store_dest(c, &instr->dest, 0,
3449 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->line_x));
3453 ntq_store_dest(c, &instr->dest, 0,
3458 ntq_store_dest(c, &instr->dest, 0,
3463 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
3469 ntq_store_dest(c, &instr->dest, 0, qdest);
3476 ntq_store_dest(c, &instr->dest, 0,
3483 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->biid));
3487 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
3491 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
3495 vir_emit_tlb_color_read(c, instr);
3499 ntq_emit_load_input(c, instr);
3503 ntq_emit_per_sample_color_write(c, instr);
3507 ntq_emit_store_output(c, instr);
3511 ntq_emit_image_size(c, instr);
3532 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
3596 ntq_store_dest(c, &instr->dest, i,
3622 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, x));
3623 ntq_store_dest(c, &instr->dest, 1, vir_MOV(c, y));
3624 ntq_store_dest(c, &instr->dest, 2, vir_MOV(c, z));
3629 ntq_store_dest(c, &instr->dest, 0,
3640 ntq_store_dest(c, &instr->dest, 0,
3658 assert(nir_src_is_const(instr->src[1]));
3660 nir_intrinsic_io_semantics(instr).location +
3661 nir_src_as_uint(instr->src[1]);
3662 uint32_t component = nir_intrinsic_component(instr);
3676 struct qreg col = ntq_get_src(c, instr->src[0], 0);
3677 for (int i = 0; i < instr->num_components; i++) {
3679 ntq_store_dest(c, &instr->dest, i,
3696 ntq_store_dest(c, &instr->dest, 0,
3702 ntq_store_dest(c, &instr->dest, 0, vir_IID(c));
3706 ntq_store_dest(c, &instr->dest, 0,
3711 ntq_store_dest(c, &instr->dest, 0, vir_SAMPID(c));
3715 ntq_store_dest(c, &instr->dest, 0,
3717 ntq_store_dest(c, &instr->dest, 1,
3722 ntq_store_dest(c, &instr->dest, 0,
3723 vir_MOV(c, ntq_get_src(c, instr->src[0], 0)));
3724 ntq_store_dest(c, &instr->dest, 1,
3725 vir_MOV(c, ntq_get_src(c, instr->src[0], 1)));
3729 ntq_store_dest(c, &instr->dest, 0, vir_uniform_f(c, 0.0f));
3730 ntq_store_dest(c, &instr->dest, 1, vir_uniform_f(c, 0.0f));
3735 ntq_store_dest(c, &instr->dest, 0, vir_uniform_f(c, 0.0f));
3736 ntq_store_dest(c, &instr->dest, 1, vir_uniform_f(c, 0.0f));
3741 struct qreg sample_idx = ntq_get_src(c, instr->src[0], 0);
3744 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, offset_x));
3745 ntq_store_dest(c, &instr->dest, 1, vir_MOV(c, offset_y));
3755 ntq_store_dest(c, &instr->dest, 0,
3757 ntq_store_dest(c, &instr->dest, 1,
3765 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, offset_x));
3766 ntq_store_dest(c, &instr->dest, 1, vir_MOV(c, offset_y));
3771 assert(nir_src_is_const(instr->src[1]));
3772 const uint32_t offset = nir_src_as_uint(instr->src[1]);
3774 for (int i = 0; i < instr->num_components; i++) {
3776 (nir_intrinsic_base(instr) + offset) * 4 +
3777 nir_intrinsic_component(instr) + i;
3785 ntq_store_dest(c, &instr->dest, i,
3797 struct qreg offset_x = ntq_get_src(c, instr->src[0], 0);
3798 struct qreg offset_y = ntq_get_src(c, instr->src[0], 1);
3804 ntq_store_dest(c, &instr->dest, i, result);
3810 ntq_store_dest(c, &instr->dest, 0,
3815 ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c));
3827 ntq_store_dest(c, &instr->dest, 0, result);
3836 ntq_store_dest(c, &instr->dest, 0,
3842 nir_print_instr(&instr->instr, stderr);
4126 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
4128 switch (instr->type) {
4130 ntq_emit_alu(c, nir_instr_as_alu(instr));
4134 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
4138 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
4146 ntq_emit_tex(c, nir_instr_as_tex(instr));
4155 ntq_emit_jump(c, nir_instr_as_jump(instr));
4157 ntq_emit_uniform_jump(c, nir_instr_as_jump(instr));
4161 fprintf(stderr, "Unknown NIR instr type: ");
4162 nir_print_instr(instr, stderr);
4171 nir_foreach_instr(instr, block) {
4172 ntq_emit_instr(c, instr);