Lines Matching defs:device
75 si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs)
77 const struct radeon_info *info = &device->physical_device->rad_info;
85 S_00B834_DATA(device->physical_device->rad_info.address32_hi >> 8));
93 if (device->physical_device->rad_info.gfx_level >= GFX7) {
99 if (device->border_color_data.bo) {
100 uint64_t bc_va = radv_buffer_get_va(device->border_color_data.bo);
108 if (device->physical_device->rad_info.gfx_level >= GFX9 &&
109 device->physical_device->rad_info.gfx_level < GFX11) {
111 device->physical_device->rad_info.gfx_level >= GFX10 ? 0x20 : 0);
114 if (device->physical_device->rad_info.gfx_level >= GFX10) {
128 if (device->physical_device->rad_info.gfx_level <= GFX6) {
134 if (device->border_color_data.bo) {
135 uint64_t bc_va = radv_buffer_get_va(device->border_color_data.bo);
140 if (device->tma_bo) {
143 assert(device->physical_device->rad_info.gfx_level == GFX8);
145 tba_va = radv_trap_handler_shader_get_va(device->trap_handler_shader);
146 tma_va = radv_buffer_get_va(device->tma_bo);
155 if (device->physical_device->rad_info.gfx_level >= GFX11) {
156 uint32_t spi_cu_en = device->physical_device->rad_info.spi_cu_en;
197 si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
199 struct radv_physical_device *physical_device = device->physical_device;
317 if (device->physical_device->rad_info.gfx_level >= GFX10) {
319 S_00B524_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
321 S_00B324_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
322 } else if (device->physical_device->rad_info.gfx_level == GFX9) {
324 S_00B414_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
326 S_00B214_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
329 S_00B524_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
331 S_00B324_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
334 if (device->physical_device->rad_info.gfx_level < GFX11)
336 S_00B124_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
428 unsigned no_alloc = device->physical_device->rad_info.gfx_level >= GFX11
449 if (device->physical_device->rad_info.gfx_level >= GFX11) {
528 if (device->border_color_data.bo) {
529 uint64_t border_color_va = radv_buffer_get_va(device->border_color_data.bo);
592 if (device->tma_bo) {
595 assert(device->physical_device->rad_info.gfx_level == GFX8);
597 tba_va = radv_trap_handler_shader_get_va(device->trap_handler_shader);
598 tma_va = radv_buffer_get_va(device->tma_bo);
627 si_emit_compute(device, cs);
631 cik_create_gfx_config(struct radv_device *device)
633 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, AMD_IP_GFX);
637 si_emit_graphics(device, cs);
640 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
647 device->ws->buffer_create(device->ws, cs->cdw * 4, 4096, device->ws->cs_domain(device->ws),
650 RADV_BO_PRIORITY_CS, 0, &device->gfx_init);
654 void *map = device->ws->buffer_map(device->gfx_init);
656 device->ws->buffer_destroy(device->ws, device->gfx_init);
657 device->gfx_init = NULL;
662 device->ws->buffer_unmap(device->gfx_init);
663 device->gfx_init_size_dw = cs->cdw;
665 device->ws->cs_destroy(cs);
808 enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level;
809 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
810 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
842 if (cmd_buffer->device->physical_device->rad_info.max_se < 4 ||
846 (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
1444 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1446 si_cs_emit_cache_flush(cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
1451 if (unlikely(cmd_buffer->device->trace_bo))
1490 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
1532 si_cs_emit_cp_dma(struct radv_device *device, struct radeon_cmdbuf *cs, bool predicating,
1537 assert(size <= cp_dma_max_byte_count(device->physical_device->rad_info.gfx_level));
1539 radeon_check_space(device->ws, cs, 9);
1540 if (device->physical_device->rad_info.gfx_level >= GFX9)
1549 if (device->physical_device->rad_info.gfx_level >= GFX9)
1559 if (device->physical_device->rad_info.gfx_level >= GFX9 && !(flags & CP_DMA_CLEAR) &&
1570 if (device->physical_device->rad_info.gfx_level >= GFX7) {
1595 struct radv_device *device = cmd_buffer->device;
1598 si_cs_emit_cp_dma(device, cs, predicating, dst_va, src_va, size, flags);
1615 if (unlikely(cmd_buffer->device->trace_bo))
1620 si_cs_cp_dma_prefetch(const struct radv_device *device, struct radeon_cmdbuf *cs, uint64_t va,
1623 struct radeon_winsys *ws = device->ws;
1624 enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
1662 si_cs_cp_dma_prefetch(cmd_buffer->device, cmd_buffer->cs, va, size,
1665 if (unlikely(cmd_buffer->device->trace_bo))
1714 enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level;
1721 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1722 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1748 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
1794 enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level;
1803 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
1826 if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX7)
1940 radv_get_sample_position(struct radv_device *device, unsigned sample_count, unsigned sample_index,
1966 radv_device_init_msaa(struct radv_device *device)
1970 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1973 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1975 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1977 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);