Lines Matching refs:nir
23 #include "nir/nir.h"
24 #include "nir/nir_xfb_info.h"
37 gather_intrinsic_load_input_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
40 switch (nir->info.stage) {
55 gather_intrinsic_store_output_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
67 switch (nir->info.stage) {
89 gather_push_constant_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
108 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
167 gather_push_constant_info(nir, instr, info);
195 gather_intrinsic_load_input_info(nir, instr, info);
198 gather_intrinsic_store_output_info(nir, instr, info);
212 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr, struct radv_shader_info *info)
229 gather_info_block(const nir_shader *nir, const nir_block *block, struct radv_shader_info *info)
234 gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info);
237 gather_tex_info(nir, nir_instr_as_tex(instr), info);
246 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
288 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
328 gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
331 switch (nir->info.stage) {
333 gather_info_input_decl_vs(nir, var, key, info);
336 gather_info_input_decl_ps(nir, var, info);
344 gather_info_output_decl_gs(const nir_shader *nir, const nir_variable *var,
358 get_vs_output_info(const nir_shader *nir, struct radv_shader_info *info)
361 switch (nir->info.stage) {
383 gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
386 switch (nir->info.stage) {
390 gather_info_output_decl_gs(nir, var, info);
400 gather_xfb_info(const nir_shader *nir, struct radv_shader_info *info)
404 if (!nir->xfb_info)
407 const nir_xfb_info *xfb = nir->xfb_info;
457 radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir,
462 struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
465 (layout->dynamic_shader_stages & mesa_to_vk_shader_stage(nir->info.stage))) {
470 if (nir->info.stage == MESA_SHADER_VERTEX) {
471 if (pipeline_key->vs.dynamic_input_state && nir->info.inputs_read) {
482 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
494 nir_foreach_shader_in_variable (variable, nir)
495 gather_info_input_decl(nir, variable, pipeline_key, info);
498 gather_info_block(nir, block, info);
501 nir_foreach_shader_out_variable(variable, nir) gather_info_output_decl(nir, variable, info);
503 if (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL ||
504 nir->info.stage == MESA_SHADER_GEOMETRY)
505 gather_xfb_info(nir, info);
507 struct radv_vs_output_info *outinfo = get_vs_output_info(nir, info);
514 nir->info.outputs_written & nir->info.per_primitive_outputs & ~special_mask;
516 nir->info.outputs_written & ~nir->info.per_primitive_outputs & ~special_mask;
519 if (nir->info.stage == MESA_SHADER_MESH && pipeline_key->has_multiview_view_index) {
536 outinfo->clip_dist_mask = (1 << nir->info.clip_distance_array_size) - 1;
537 outinfo->cull_dist_mask = (1 << nir->info.cull_distance_array_size) - 1;
538 outinfo->cull_dist_mask <<= nir->info.clip_distance_array_size;
580 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
581 uint64_t per_primitive_input_mask = nir->info.inputs_read & nir->info.per_primitive_inputs;
583 assert(num_per_primitive_inputs <= nir->num_inputs);
585 info->ps.num_interp = nir->num_inputs - num_per_primitive_inputs;
589 info->vs.needs_draw_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
590 info->vs.needs_base_instance |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE);
591 info->vs.needs_instance_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
592 info->uses_view_index |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VIEW_INDEX);
593 info->uses_invocation_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INVOCATION_ID);
594 info->uses_prim_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
597 info->cs.uses_grid_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_WORKGROUPS);
598 info->cs.uses_local_invocation_idx = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
599 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SUBGROUP_ID) |
600 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_SUBGROUPS);
601 switch (nir->info.stage) {
605 info->cs.block_size[i] = nir->info.workgroup_size[i];
606 info->cs.uses_ray_launch_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_RAY_LAUNCH_SIZE_ADDR_AMD);
611 if (nir->info.stage == MESA_SHADER_TASK) {
614 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_WORKGROUP_ID);
627 info->ps.can_discard = nir->info.fs.uses_discard;
628 info->ps.early_fragment_test = nir->info.fs.early_fragment_tests;
629 info->ps.post_depth_coverage = nir->info.fs.post_depth_coverage;
630 info->ps.depth_layout = nir->info.fs.depth_layout;
631 info->ps.uses_sample_shading = nir->info.fs.uses_sample_shading;
632 info->ps.writes_memory = nir->info.writes_memory;
633 info->ps.has_pcoord = nir->info.inputs_read & VARYING_BIT_PNTC;
634 info->ps.prim_id_input = nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID;
635 info->ps.layer_input = nir->info.inputs_read & VARYING_BIT_LAYER;
636 info->ps.viewport_index_input = nir->info.inputs_read & VARYING_BIT_VIEWPORT;
637 info->ps.writes_z = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH);
638 info->ps.writes_stencil = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL);
639 info->ps.writes_sample_mask = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK);
640 info->ps.reads_sample_mask_in = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
641 info->ps.reads_sample_id = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID);
642 info->ps.reads_frag_shading_rate = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_SHADING_RATE);
643 info->ps.reads_front_face = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE);
644 info->ps.reads_barycentric_model = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_PULL_MODEL);
647 info->gs.vertices_in = nir->info.gs.vertices_in;
648 info->gs.vertices_out = nir->info.gs.vertices_out;
649 info->gs.output_prim = nir->info.gs.output_primitive;
650 info->gs.invocations = nir->info.gs.invocations;
652 nir->info.gs.active_stream_mask ? util_last_bit(nir->info.gs.active_stream_mask) - 1 : 0;
655 info->tes._primitive_mode = nir->info.tess._primitive_mode;
656 info->tes.spacing = nir->info.tess.spacing;
657 info->tes.ccw = nir->info.tess.ccw;
658 info->tes.point_mode = nir->info.tess.point_mode;
661 info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
666 info->ms.output_prim = nir->info.mesh.primitive_type;
672 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
674 nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4;
675 info->gs.gsvs_vertex_size = (util_bitcount64(nir->info.outputs_written) + add_clip) * 16;
676 info->gs.max_gsvs_emit_size = info->gs.gsvs_vertex_size * nir->info.gs.vertices_out;
680 if ((nir->info.stage == MESA_SHADER_VERTEX && info->vs.as_es) ||
681 (nir->info.stage == MESA_SHADER_TESS_EVAL && info->tes.as_es)) {
683 nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
684 uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
690 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
700 info->ps.writes_memory || nir->info.fs.needs_quad_helper_invocations ||
701 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) ||
702 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_POINT_COORD) ||
703 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
704 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS) ||
705 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN) ||
706 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_HELPER_INVOCATION));