Lines Matching refs:info
31 mark_sampler_desc(const nir_variable *var, struct radv_shader_info *info)
33 info->desc_set_used_mask |= (1u << var->data.descriptor_set);
38 struct radv_shader_info *info)
40 switch (nir->info.stage) {
46 info->vs.input_usage_mask[idx] |= mask << component;
56 struct radv_shader_info *info)
67 switch (nir->info.stage) {
69 output_usage_mask = info->vs.output_usage_mask;
72 output_usage_mask = info->tes.output_usage_mask;
75 output_usage_mask = info->gs.output_usage_mask;
90 struct radv_shader_info *info)
92 info->loads_push_constants = true;
99 info->inline_push_constant_mask |= u_bit_consecutive64(start, size);
104 info->can_inline_all_push_constants = false;
109 struct radv_shader_info *info)
124 info->ps.reads_persp_center = true;
126 info->ps.reads_persp_centroid = true;
128 info->ps.reads_persp_sample = true;
134 info->ps.reads_linear_center = true;
136 info->ps.reads_linear_centroid = true;
138 info->ps.reads_linear_sample = true;
144 info->ps.needs_sample_positions = true;
154 info->cs.uses_block_id[i] = true;
156 info->cs.uses_thread_id[i] = true;
161 info->ps.reads_frag_coord_mask |= nir_ssa_def_components_read(&instr->dest.ssa);
164 info->ps.reads_sample_pos_mask |= nir_ssa_def_components_read(&instr->dest.ssa);
167 gather_push_constant_info(nir, instr, info);
170 info->desc_set_used_mask |= (1u << nir_intrinsic_desc_set(instr));
191 mark_sampler_desc(var, info);
195 gather_intrinsic_load_input_info(nir, instr, info);
198 gather_intrinsic_store_output_info(nir, instr, info);
201 info->cs.uses_sbt = true;
204 info->force_vrs_per_vertex = true;
212 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr, struct radv_shader_info *info)
217 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
220 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
229 gather_info_block(const nir_shader *nir, const nir_block *block, struct radv_shader_info *info)
234 gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info);
237 gather_tex_info(nir, nir_instr_as_tex(instr), info);
247 const struct radv_pipeline_key *key, struct radv_shader_info *info)
255 info->vs.needs_instance_id = true;
256 info->vs.needs_base_instance = true;
259 if (info->vs.use_per_attribute_vb_descs)
260 info->vs.vb_desc_usage_mask |= 1u << attrib_index;
262 info->vs.vb_desc_usage_mask |= 1u << key->vs.vertex_attribute_bindings[attrib_index];
267 mark_16bit_ps_input(struct radv_shader_info *info, const struct glsl_type *type, int location)
272 info->ps.float16_shaded_mask |= ((1ull << attrib_count) - 1) << location;
277 mark_16bit_ps_input(info, glsl_get_array_element(type), location + i * stride);
282 mark_16bit_ps_input(info, glsl_get_struct_field(type, i), location);
289 struct radv_shader_info *info)
297 info->ps.num_input_clips_culls += attrib_count;
307 mark_16bit_ps_input(info, var->type, var->data.driver_location);
314 info->ps.flat_shaded_mask |= mask << var->data.driver_location;
316 info->ps.explicit_shaded_mask |= mask << var->data.driver_location;
321 info->ps.input_per_primitive_mask |= mask << (var->data.location - VARYING_SLOT_VAR0);
323 info->ps.input_mask |= mask << (var->data.location - VARYING_SLOT_VAR0);
329 const struct radv_pipeline_key *key, struct radv_shader_info *info)
331 switch (nir->info.stage) {
333 gather_info_input_decl_vs(nir, var, key, info);
336 gather_info_input_decl_ps(nir, var, info);
345 struct radv_shader_info *info)
353 info->gs.num_stream_output_components[stream] += num_components;
354 info->gs.output_streams[idx] = stream;
358 get_vs_output_info(const nir_shader *nir, struct radv_shader_info *info)
361 switch (nir->info.stage) {
363 if (!info->vs.as_ls && !info->vs.as_es)
364 return &info->vs.outinfo;
367 return &info->vs.outinfo;
370 if (!info->tes.as_es)
371 return &info->tes.outinfo;
374 return &info->ms.outinfo;
384 struct radv_shader_info *info)
386 switch (nir->info.stage) {
390 gather_info_output_decl_gs(nir, var, info);
400 gather_xfb_info(const nir_shader *nir, struct radv_shader_info *info)
402 struct radv_streamout_info *so = &info->so;
450 radv_nir_shader_info_init(struct radv_shader_info *info)
453 info->can_inline_all_push_constants = true;
460 struct radv_shader_info *info)
465 (layout->dynamic_shader_stages & mesa_to_vk_shader_stage(nir->info.stage))) {
466 info->loads_push_constants = true;
467 info->loads_dynamic_offsets = true;
470 if (nir->info.stage == MESA_SHADER_VERTEX) {
471 if (pipeline_key->vs.dynamic_input_state && nir->info.inputs_read) {
472 info->vs.has_prolog = true;
473 info->vs.dynamic_inputs = true;
479 info->vs.use_per_attribute_vb_descs = device->robust_buffer_access || info->vs.dynamic_inputs;
482 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
484 info->ps.has_epilog = true;
490 info->vs.needs_instance_id |= info->vs.has_prolog;
491 info->vs.needs_base_instance |= info->vs.has_prolog;
492 info->vs.needs_draw_id |= info->vs.has_prolog;
495 gather_info_input_decl(nir, variable, pipeline_key, info);
498 gather_info_block(nir, block, info);
501 nir_foreach_shader_out_variable(variable, nir) gather_info_output_decl(nir, variable, info);
503 if (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL ||
504 nir->info.stage == MESA_SHADER_GEOMETRY)
505 gather_xfb_info(nir, info);
507 struct radv_vs_output_info *outinfo = get_vs_output_info(nir, info);
514 nir->info.outputs_written & nir->info.per_primitive_outputs & ~special_mask;
516 nir->info.outputs_written & ~nir->info.per_primitive_outputs & ~special_mask;
519 if (nir->info.stage == MESA_SHADER_MESH && pipeline_key->has_multiview_view_index) {
521 info->uses_view_index = true;
536 outinfo->clip_dist_mask = (1 << nir->info.clip_distance_array_size) - 1;
537 outinfo->cull_dist_mask = (1 << nir->info.cull_distance_array_size) - 1;
538 outinfo->cull_dist_mask <<= nir->info.clip_distance_array_size;
580 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
581 uint64_t per_primitive_input_mask = nir->info.inputs_read & nir->info.per_primitive_inputs;
585 info->ps.num_interp = nir->num_inputs - num_per_primitive_inputs;
586 info->ps.num_prim_interp = num_per_primitive_inputs;
589 info->vs.needs_draw_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
590 info->vs.needs_base_instance |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE);
591 info->vs.needs_instance_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
592 info->uses_view_index |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VIEW_INDEX);
593 info->uses_invocation_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INVOCATION_ID);
594 info->uses_prim_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
597 info->cs.uses_grid_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_WORKGROUPS);
598 info->cs.uses_local_invocation_idx = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
599 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SUBGROUP_ID) |
600 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_SUBGROUPS);
601 switch (nir->info.stage) {
605 info->cs.block_size[i] = nir->info.workgroup_size[i];
606 info->cs.uses_ray_launch_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_RAY_LAUNCH_SIZE_ADDR_AMD);
611 if (nir->info.stage == MESA_SHADER_TASK) {
613 info->vs.needs_draw_id |=
614 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_WORKGROUP_ID);
617 info->cs.uses_block_id[0] = true;
618 info->cs.uses_block_id[1] = true;
619 info->cs.uses_block_id[2] = true;
620 info->cs.uses_grid_size = true;
623 info->cs.uses_local_invocation_idx = true;
627 info->ps.can_discard = nir->info.fs.uses_discard;
628 info->ps.early_fragment_test = nir->info.fs.early_fragment_tests;
629 info->ps.post_depth_coverage = nir->info.fs.post_depth_coverage;
630 info->ps.depth_layout = nir->info.fs.depth_layout;
631 info->ps.uses_sample_shading = nir->info.fs.uses_sample_shading;
632 info->ps.writes_memory = nir->info.writes_memory;
633 info->ps.has_pcoord = nir->info.inputs_read & VARYING_BIT_PNTC;
634 info->ps.prim_id_input = nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID;
635 info->ps.layer_input = nir->info.inputs_read & VARYING_BIT_LAYER;
636 info->ps.viewport_index_input = nir->info.inputs_read & VARYING_BIT_VIEWPORT;
637 info->ps.writes_z = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH);
638 info->ps.writes_stencil = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL);
639 info->ps.writes_sample_mask = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK);
640 info->ps.reads_sample_mask_in = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
641 info->ps.reads_sample_id = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID);
642 info->ps.reads_frag_shading_rate = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_SHADING_RATE);
643 info->ps.reads_front_face = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE);
644 info->ps.reads_barycentric_model = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_PULL_MODEL);
647 info->gs.vertices_in = nir->info.gs.vertices_in;
648 info->gs.vertices_out = nir->info.gs.vertices_out;
649 info->gs.output_prim = nir->info.gs.output_primitive;
650 info->gs.invocations = nir->info.gs.invocations;
651 info->gs.max_stream =
652 nir->info.gs.active_stream_mask ? util_last_bit(nir->info.gs.active_stream_mask) - 1 : 0;
655 info->tes._primitive_mode = nir->info.tess._primitive_mode;
656 info->tes.spacing = nir->info.tess.spacing;
657 info->tes.ccw = nir->info.tess.ccw;
658 info->tes.point_mode = nir->info.tess.point_mode;
661 info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
666 info->ms.output_prim = nir->info.mesh.primitive_type;
672 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
674 nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4;
675 info->gs.gsvs_vertex_size = (util_bitcount64(nir->info.outputs_written) + add_clip) * 16;
676 info->gs.max_gsvs_emit_size = info->gs.gsvs_vertex_size * nir->info.gs.vertices_out;
680 if ((nir->info.stage == MESA_SHADER_VERTEX && info->vs.as_es) ||
681 (nir->info.stage == MESA_SHADER_TESS_EVAL && info->tes.as_es)) {
683 nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
684 uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
685 ? info->vs.num_linked_outputs
686 : info->tes.num_linked_outputs;
690 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
691 bool uses_persp_or_linear_interp = info->ps.reads_persp_center ||
692 info->ps.reads_persp_centroid ||
693 info->ps.reads_persp_sample ||
694 info->ps.reads_linear_center ||
695 info->ps.reads_linear_centroid ||
696 info->ps.reads_linear_sample;
698 info->ps.allow_flat_shading =
699 !(uses_persp_or_linear_interp || info->ps.needs_sample_positions ||
700 info->ps.writes_memory || nir->info.fs.needs_quad_helper_invocations ||
701 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) ||
702 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_POINT_COORD) ||
703 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) ||
704 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS) ||
705 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN) ||
706 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_HELPER_INVOCATION));
708 info->ps.spi_ps_input = radv_compute_spi_ps_input(pipeline_key, info);