Lines Matching refs:info
143 return nir && nir->info.internal;
221 if (shader->info.stage == MESA_SHADER_FRAGMENT &&
222 (shader->info.fs.uses_discard || shader->info.fs.uses_demote)) {
431 if (nir->info.stage == MESA_SHADER_MESH) {
441 if (nir->info.stage == MESA_SHADER_VERTEX)
444 if (nir->info.stage == MESA_SHADER_VERTEX && progress)
503 nir->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_SHADING_RATE);
506 if (nir->info.stage == MESA_SHADER_VERTEX)
510 if (nir->info.stage == MESA_SHADER_VERTEX && progress)
526 const struct radv_shader_info *info = &fs_stage->info;
546 if (info->ps.uses_sample_shading) {
793 nir->info.internal |= device->app_shaders_internal;
794 assert(nir->info.stage == stage->stage);
844 if (nir->info.stage == MESA_SHADER_FRAGMENT)
846 if (nir->info.stage == MESA_SHADER_FRAGMENT)
870 if (nir->info.stage == MESA_SHADER_VERTEX ||
871 nir->info.stage == MESA_SHADER_TESS_EVAL ||
872 nir->info.stage == MESA_SHADER_GEOMETRY)
897 .lower_cs_local_id_to_index = nir->info.stage == MESA_SHADER_MESH,
898 .lower_local_invocation_index = nir->info.stage == MESA_SHADER_COMPUTE &&
899 ((nir->info.workgroup_size[0] == 1) +
900 (nir->info.workgroup_size[1] == 1) +
901 (nir->info.workgroup_size[2] == 1)) == 2,
905 if (nir->info.stage == MESA_SHADER_MESH) {
919 nir->info.separate_shader = true;
923 if (nir->info.ray_queries > 0) {
949 if (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_GEOMETRY ||
950 nir->info.stage == MESA_SHADER_FRAGMENT) {
952 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
1011 if (nir->info.stage == MESA_SHADER_COMPUTE ||
1012 nir->info.stage == MESA_SHADER_TASK ||
1013 nir->info.stage == MESA_SHADER_MESH) {
1016 if (nir->info.stage == MESA_SHADER_TASK ||
1017 nir->info.stage == MESA_SHADER_MESH)
1020 if (!nir->info.shared_memory_explicit_layout) {
1025 if (nir->info.zero_initialize_shared_memory && nir->info.shared_size > 0) {
1027 const unsigned shared_size = ALIGN(nir->info.shared_size, chunk_size);
1042 if ((nir->info.stage == MESA_SHADER_VERTEX ||
1043 nir->info.stage == MESA_SHADER_GEOMETRY ||
1044 nir->info.stage == MESA_SHADER_MESH) &&
1045 nir->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_SHADING_RATE)) {
1057 !key->optimisations_disabled && nir->info.stage != MESA_SHADER_COMPUTE) {
1121 nir->info.inputs_read |= VARYING_BIT_LAYER;
1123 nir->info.per_primitive_inputs |= VARYING_BIT_LAYER;
1141 if (nir->info.stage == MESA_SHADER_COMPUTE)
1144 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1162 const struct radv_shader_info *info = &stage->info;
1165 if (nir->info.stage == MESA_SHADER_VERTEX) {
1166 if (info->vs.as_ls) {
1167 NIR_PASS_V(nir, ac_nir_lower_ls_outputs_to_mem, NULL, info->vs.tcs_in_out_eq,
1168 info->vs.tcs_temp_only_input_mask);
1170 } else if (info->vs.as_es) {
1173 info->vs.num_linked_outputs * 16u);
1176 } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
1177 NIR_PASS_V(nir, ac_nir_lower_hs_inputs_to_mem, NULL, info->vs.tcs_in_out_eq);
1180 info->tcs.tes_reads_tess_factors, info->tcs.tes_inputs_read,
1181 info->tcs.tes_patch_inputs_read, info->tcs.num_linked_outputs,
1182 info->tcs.num_linked_patch_outputs, info->wave_size,
1186 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
1189 if (info->tes.as_es) {
1192 info->tes.num_linked_outputs * 16u);
1196 } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
1200 } else if (nir->info.stage == MESA_SHADER_TASK) {
1205 } else if (nir->info.stage == MESA_SHADER_MESH) {
1216 unsigned num_vertices_per_primitive, const struct radv_shader_info *info)
1223 if (nir->info.outputs_written & (VARYING_BIT_VIEWPORT | VARYING_BIT_VIEWPORT_MASK))
1227 if (info->vs.has_prolog)
1234 * Estimate an upper limit for PS input param count based on GPU info.
1259 if (nir->info.writes_memory)
1265 if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SUBGROUP_INVOCATION))
1274 const struct radv_shader_info *info = &ngg_stage->info;
1277 assert(nir->info.stage == MESA_SHADER_VERTEX ||
1278 nir->info.stage == MESA_SHADER_TESS_EVAL ||
1279 nir->info.stage == MESA_SHADER_GEOMETRY ||
1280 nir->info.stage == MESA_SHADER_MESH);
1282 const struct gfx10_ngg_info *ngg_info = &info->ngg_info;
1286 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
1287 if (nir->info.tess.point_mode)
1289 else if (nir->info.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES)
1293 if (info->tes.outinfo.export_prim_id)
1294 BITSET_SET(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
1296 } else if (nir->info.stage == MESA_SHADER_VERTEX) {
1302 BITSET_SET(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
1304 } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
1305 num_vertices_per_prim = nir->info.gs.vertices_in;
1306 } else if (nir->info.stage == MESA_SHADER_MESH) {
1307 if (nir->info.mesh.primitive_type == SHADER_PRIM_POINTS)
1309 else if (nir->info.mesh.primitive_type == SHADER_PRIM_LINES)
1312 assert(nir->info.mesh.primitive_type == SHADER_PRIM_TRIANGLES);
1320 if (nir->info.stage == MESA_SHADER_VERTEX ||
1321 nir->info.stage == MESA_SHADER_TESS_EVAL) {
1324 assert(info->is_ngg);
1326 if (info->has_ngg_culling)
1329 if (nir->info.stage == MESA_SHADER_VERTEX) {
1330 export_prim_id = info->vs.outinfo.export_prim_id;
1332 export_prim_id = info->tes.outinfo.export_prim_id;
1338 info->workgroup_size, info->wave_size, info->has_ngg_culling,
1339 info->has_ngg_early_prim_export, info->is_ngg_passthrough, export_prim_id,
1344 ngg_stage->info.ngg_info.esgs_ring_size = nir->info.shared_size;
1345 } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
1346 assert(info->is_ngg);
1347 NIR_PASS_V(nir, ac_nir_lower_ngg_gs, info->wave_size, info->workgroup_size,
1348 info->ngg_info.esgs_ring_size, info->gs.gsvs_vertex_size,
1349 info->ngg_info.ngg_emit_size * 4u, pl_key->vs.provoking_vtx_last);
1350 } else if (nir->info.stage == MESA_SHADER_MESH) {
1352 NIR_PASS_V(nir, ac_nir_lower_ngg_ms, &scratch_ring, info->wave_size, pl_key->has_multiview_view_index);
1353 ngg_stage->info.ms.needs_ms_scratch_ring = scratch_ring;
1626 const struct radv_shader_info *info)
1634 return chip == GFX10 || (chip >= GFX10_3 && !info->is_ngg);
1637 return chip == GFX10 && info->is_ngg;
1645 const struct radv_shader_info *info, gl_shader_stage stage,
1686 S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) | S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
1687 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) | S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
1688 S_00B12C_SO_EN(!!info->so.num_outputs);
1691 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / (info->wave_size == 32 ? 8 : 4)) |
1701 bool wgp_mode = radv_should_use_wgp_mode(device, stage, info);
1705 if (info->is_ngg) {
1708 } else if (info->tes.as_es) {
1710 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
1714 bool enable_prim_id = info->tes.outinfo.export_prim_id || info->uses_prim_id;
1729 if (info->vs.needs_instance_id) {
1735 S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks) | S_00B42C_EXCP_EN_GFX6(excp_en);
1737 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
1739 S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks) | S_00B42C_EXCP_EN_GFX9(excp_en);
1749 if (info->is_ngg) {
1751 } else if (info->vs.as_ls) {
1757 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
1758 } else if (info->vs.as_es) {
1761 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
1767 if (info->vs.needs_instance_id && pdevice->rad_info.gfx_level >= GFX10) {
1769 } else if (info->vs.outinfo.export_prim_id) {
1771 } else if (info->vs.needs_instance_id) {
1801 config_out->rsrc2 |= S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
1802 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
1803 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
1804 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2
1805 : info->cs.uses_thread_id[1] ? 1
1807 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
1817 if (pdevice->rad_info.gfx_level >= GFX10 && info->is_ngg &&
1823 es_stage = info->gs.es_type;
1827 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
1829 bool enable_prim_id = info->tes.outinfo.export_prim_id || info->uses_prim_id;
1844 bool need_gs_vtx_offset2 = !info->is_ngg_passthrough || info->gs.vertices_in >= 3;
1848 need_gs_vtx_offset2 &= info->tes._primitive_mode == TESS_PRIMITIVE_TRIANGLES ||
1849 info->tes._primitive_mode == TESS_PRIMITIVE_QUADS;
1851 if (info->uses_invocation_id) {
1853 } else if (info->uses_prim_id || (es_stage == MESA_SHADER_VERTEX &&
1854 info->vs.outinfo.export_prim_id)) {
1872 unsigned es_type = info->gs.es_type;
1877 if (info->vs.needs_instance_id) {
1883 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
1891 if (info->uses_invocation_id) {
1893 } else if (info->uses_prim_id) {
1895 } else if (info->gs.vertices_in >= 3) {
1923 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
1927 sym->size = binary->info.ngg_info.esgs_ring_size;
1931 if (binary->info.is_ngg && binary->stage == MESA_SHADER_GEOMETRY) {
1934 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
1944 .info = &device->physical_device->rad_info,
1946 .wave_size = binary->info.wave_size,
1973 struct ac_rtld_upload_info info = {
1979 if (!ac_rtld_upload(&info)) {
2038 config.lds_size = binary->info.tcs.num_lds_blocks;
2041 assert(!binary->info.has_ngg_culling || config.lds_size);
2055 shader->info = binary->info;
2062 radv_postprocess_config(device, &config, &binary->info, binary->stage, args, &shader->config);
2197 struct radv_shader_info *info, const struct radv_shader_args *args,
2231 llvm_compile_shader(options, info, shader_count, shaders, &binary, args);
2239 radv_aco_convert_shader_info(&ac_info, info);
2243 binary->info = *info;
2252 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
2254 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
2276 gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
2283 options.wgp_mode = radv_should_use_wgp_mode(device, stage, &pl_stage->info);
2285 return shader_compile(device, shaders, shader_count, stage, &pl_stage->info,
2292 struct radv_shader_info *info, const struct radv_shader_args *args,
2301 return shader_compile(device, &shader, 1, stage, info, args, &options, true, false,
2311 struct radv_shader_info info = {0};
2321 options.wgp_mode = radv_should_use_wgp_mode(device, MESA_SHADER_COMPUTE, &info);
2322 info.wave_size = 64;
2327 radv_declare_shader_args(device->physical_device->rad_info.gfx_level, &key, &info,
2330 shader = shader_compile(device, &b.shader, 1, MESA_SHADER_COMPUTE, &info, &args, &options,
2436 struct radv_shader_info info = {0};
2437 info.wave_size = key->wave32 ? 32 : 64;
2438 info.vs.needs_instance_id = true;
2439 info.vs.needs_base_instance = true;
2440 info.vs.needs_draw_id = true;
2441 info.vs.use_per_attribute_vb_descs = true;
2442 info.vs.vb_desc_usage_mask = BITFIELD_MASK(key->num_attributes);
2443 info.vs.has_prolog = true;
2444 info.vs.as_ls = key->as_ls;
2445 info.is_ngg = key->is_ngg;
2450 radv_declare_shader_args(options.gfx_level, &pipeline_key, &info, key->next_stage,
2453 info.user_sgprs_locs = args.user_sgprs_locs;
2454 info.inline_push_constant_mask = args.ac.inline_push_const_mask;
2465 radv_aco_convert_shader_info(&ac_info, &info);
2470 struct radv_shader_part *prolog = upload_shader_part(device, binary, info.wave_size);
2500 struct radv_shader_info info = {0};
2501 info.wave_size = key->wave32 ? 32 : 64;
2502 info.workgroup_size = 64;
2515 radv_aco_convert_shader_info(&ac_info, &info);
2520 struct radv_shader_part *epilog = upload_shader_part(device, binary, info.wave_size);
2605 radv_get_shader_name(const struct radv_shader_info *info, gl_shader_stage stage)
2609 if (info->vs.as_ls)
2611 else if (info->vs.as_es)
2613 else if (info->is_ngg)
2620 if (info->tes.as_es)
2622 else if (info->is_ngg)
2645 struct radeon_info *info = &device->physical_device->rad_info;
2646 enum amd_gfx_level gfx_level = info->gfx_level;
2647 uint8_t wave_size = shader->info.wave_size;
2652 max_simd_waves = info->max_wave64_per_simd * (64 / wave_size);
2656 conf->lds_size * info->lds_encode_granularity + shader->info.ps.num_interp * 48;
2657 lds_per_wave = align(lds_per_wave, info->lds_alloc_granularity);
2659 unsigned max_workgroup_size = shader->info.workgroup_size;
2661 align(conf->lds_size * info->lds_encode_granularity, info->lds_alloc_granularity);
2667 max_simd_waves = MIN2(max_simd_waves, info->num_physical_sgprs_per_simd / sgprs);
2671 unsigned physical_vgprs = info->num_physical_wave64_vgprs_per_simd * (64 / wave_size);
2678 unsigned simd_per_workgroup = info->num_simd_per_compute_unit;
2682 unsigned max_lds_per_simd = info->lds_size_per_workgroup / simd_per_workgroup;
2691 const struct radv_shader_info *info)
2695 spi_ps_input = S_0286CC_PERSP_CENTER_ENA(info->ps.reads_persp_center) |
2696 S_0286CC_PERSP_CENTROID_ENA(info->ps.reads_persp_centroid) |
2697 S_0286CC_PERSP_SAMPLE_ENA(info->ps.reads_persp_sample) |
2698 S_0286CC_LINEAR_CENTER_ENA(info->ps.reads_linear_center) |
2699 S_0286CC_LINEAR_CENTROID_ENA(info->ps.reads_linear_centroid) |
2700 S_0286CC_LINEAR_SAMPLE_ENA(info->ps.reads_linear_sample)|
2701 S_0286CC_PERSP_PULL_MODEL_ENA(info->ps.reads_barycentric_model) |
2702 S_0286CC_FRONT_FACE_ENA(info->ps.reads_front_face);
2704 if (info->ps.reads_frag_coord_mask ||
2705 info->ps.reads_sample_pos_mask) {
2706 uint8_t mask = info->ps.reads_frag_coord_mask | info->ps.reads_sample_pos_mask;
2713 if (pipeline_key->adjust_frag_coord_z && info->ps.reads_frag_coord_mask & (1 << 2)) {
2718 if (info->ps.reads_sample_id || info->ps.reads_frag_shading_rate || info->ps.reads_sample_mask_in) {
2722 if (info->ps.reads_sample_mask_in) {
2795 fprintf(output, "\n%s:\n", radv_get_shader_name(&shader->info, stage));