Lines Matching defs:shader
162 /* Only dump non-meta shader stats. */
167 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively, bool allow_copies)
174 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
175 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
183 NIR_PASS(progress, shader, nir_opt_find_array_copies);
186 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
187 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
188 NIR_PASS(_, shader, nir_lower_vars_to_ssa);
190 NIR_PASS(_, shader, nir_lower_alu_width, vectorize_vec2_16bit, NULL);
191 NIR_PASS(_, shader, nir_lower_phis_to_scalar, true);
193 NIR_PASS(progress, shader, nir_copy_prop);
194 NIR_PASS(progress, shader, nir_opt_remove_phis);
195 NIR_PASS(progress, shader, nir_opt_dce);
196 if (nir_opt_trivial_continues(shader)) {
198 NIR_PASS(progress, shader, nir_copy_prop);
199 NIR_PASS(progress, shader, nir_opt_remove_phis);
200 NIR_PASS(progress, shader, nir_opt_dce);
202 NIR_PASS(progress, shader, nir_opt_if,
204 NIR_PASS(progress, shader, nir_opt_dead_cf);
205 NIR_PASS(progress, shader, nir_opt_cse);
206 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
207 NIR_PASS(progress, shader, nir_opt_constant_folding);
208 NIR_PASS(progress, shader, nir_opt_algebraic);
210 NIR_PASS(progress, shader, nir_opt_undef);
212 if (shader->options->max_unroll_iterations) {
213 NIR_PASS(progress, shader, nir_opt_loop_unroll);
217 NIR_PASS(progress, shader, nir_opt_shrink_vectors);
218 NIR_PASS(progress, shader, nir_remove_dead_variables,
221 if (shader->info.stage == MESA_SHADER_FRAGMENT &&
222 (shader->info.fs.uses_discard || shader->info.fs.uses_demote)) {
223 NIR_PASS(progress, shader, nir_opt_conditional_discard);
224 NIR_PASS(progress, shader, nir_opt_move_discards_to_top);
227 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
688 * shader directly. In that case, we just ignore the SPIR-V entirely
689 * and just use the NIR shader. We don't want to alter meta and RT
692 nir_validate_shader(nir, "in internal shader");
918 /* Vulkan uses the separate-shader linking model */
1037 * section next to the shader.
1088 * shader, we also need to lower this to the gl_Layer varying. This pass
1226 /* We don't support culling with vertex shader prologs. */
1253 /* When the shader writes memory, it is difficult to guarantee correctness.
1257 * then may be okay to keep the memory stores in the 1st shader part, and delete them from the 2nd.
1262 /* When the shader relies on the subgroup invocation ID, we'd break it, because the ID changes after the culling.
1292 /* Manually mark the primitive ID used, so the shader can repack it. */
1300 /* Manually mark the instance ID used, so the shader can repack it. */
1423 /* Try to use an existing hole. Unless the shader is very large, this should only have to look
1469 /* Allocate a new shader arena. */
1678 /* Configure the shader exceptions like memory violation, etc.
1813 unreachable("unsupported shader type");
1834 unreachable("Unexpected ES shader stage");
1885 unreachable("invalid shader ES type");
1914 radv_open_rtld_binary(struct radv_device *device, const struct radv_shader *shader,
1960 struct radv_shader *shader, void *dest_ptr)
1968 if (!radv_open_rtld_binary(device, shader, binary, &rtld_binary)) {
1969 free(shader);
1975 .rx_va = radv_shader_get_va(shader),
1980 radv_shader_destroy(device, shader);
1985 shader->code_ptr = dest_ptr;
1997 shader->code_ptr = dest_ptr;
2008 struct radv_shader *shader = calloc(1, sizeof(struct radv_shader));
2009 if (!shader)
2012 shader->ref_count = 1;
2016 free(shader);
2021 if (!radv_open_rtld_binary(device, shader, binary, &rtld_binary)) {
2022 free(shader);
2028 free(shader);
2043 shader->code_size = rtld_binary.rx_size;
2044 shader->exec_size = rtld_binary.exec_size;
2050 shader->code_size =
2052 shader->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
2055 shader->info = binary->info;
2058 /* Copy the shader binary configuration from the cache. */
2059 memcpy(&shader->config, &binary->config, sizeof(shader->config));
2062 radv_postprocess_config(device, &config, &binary->info, binary->stage, args, &shader->config);
2067 free(shader);
2073 if (!radv_open_rtld_binary(device, shader, binary, &rtld_binary)) {
2074 free(shader);
2083 radv_shader_destroy(device, shader);
2088 shader->ir_string =
2090 shader->disasm_string = malloc(disasm_size + 1);
2091 memcpy(shader->disasm_string, disasm_data, disasm_size);
2092 shader->disasm_string[disasm_size] = 0;
2099 shader->ir_string =
2101 shader->disasm_string =
2107 shader->statistics = calloc(bin->stats_size, 1);
2108 memcpy(shader->statistics, bin->data, bin->stats_size);
2111 return shader;
2245 struct radv_shader *shader = radv_shader_create(device, binary, keep_shader_info, false, args);
2246 if (!shader) {
2256 fprintf(stderr, "\ndisasm:\n%s\n", shader->disasm_string);
2260 shader->nir_string = radv_dump_nir_shaders(shaders, shader_count);
2263 /* Copy the shader binary configuration to store it in the cache. */
2264 memcpy(&binary->config, &shader->config, sizeof(binary->config));
2267 return shader;
2291 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *shader,
2301 return shader_compile(device, &shader, 1, stage, info, args, &options, true, false,
2309 struct radv_shader *shader = NULL;
2330 shader = shader_compile(device, &b.shader, 1, MESA_SHADER_COMPUTE, &info, &args, &options,
2333 trap->alloc = radv_alloc_shader_memory(device, shader->code_size, NULL);
2341 ralloc_free(b.shader);
2342 free(shader);
2537 radv_shader_destroy(struct radv_device *device, struct radv_shader *shader)
2539 if (!p_atomic_dec_zero(&shader->ref_count))
2542 free(shader->spirv);
2543 free(shader->nir_string);
2544 free(shader->disasm_string);
2545 free(shader->ir_string);
2546 free(shader->statistics);
2547 free(shader);
2562 radv_shader_get_va(const struct radv_shader *shader)
2564 return shader->va;
2588 struct radv_shader *shader = pipeline->shaders[i];
2589 if (!shader)
2592 if (pc >= shader->va &&
2593 pc < shader->va + align(shader->code_size, RADV_SHADER_ALLOC_ALIGNMENT))
2594 return shader;
2637 return "Unknown shader";
2642 radv_get_max_waves(const struct radv_device *device, struct radv_shader *shader,
2647 uint8_t wave_size = shader->info.wave_size;
2648 struct ac_shader_config *conf = &shader->config;
2656 conf->lds_size * info->lds_encode_granularity + shader->info.ps.num_interp * 48;
2659 unsigned max_workgroup_size = shader->info.workgroup_size;
2743 struct radv_shader *shader = pipeline->shaders[stage];
2795 fprintf(output, "\n%s:\n", radv_get_shader_name(&shader->info, stage));