Lines Matching refs:device
65 build_occlusion_query_shader(struct radv_device *device)
106 nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "occlusion_query");
115 unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
116 unsigned db_count = device->physical_device->rad_info.max_render_backends;
197 build_pipeline_statistics_query_shader(struct radv_device *device)
241 nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "pipeline_statistics_query");
369 build_tfb_query_shader(struct radv_device *device)
406 nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "tfb_query");
495 build_timestamp_query_shader(struct radv_device *device)
527 nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "timestamp_query");
600 build_pg_query_shader(struct radv_device *device)
640 nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "pg_query");
748 radv_device_init_meta_query_state_internal(struct radv_device *device)
757 mtx_lock(&device->meta_state.mtx);
758 if (device->meta_state.query.pipeline_statistics_query_pipeline) {
759 mtx_unlock(&device->meta_state.mtx);
762 occlusion_cs = build_occlusion_query_shader(device);
763 pipeline_statistics_cs = build_pipeline_statistics_query_shader(device);
764 tfb_cs = build_tfb_query_shader(device);
765 timestamp_cs = build_timestamp_query_shader(device);
766 pg_cs = build_pg_query_shader(device);
785 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &occlusion_ds_create_info,
786 &device->meta_state.alloc,
787 &device->meta_state.query.ds_layout);
794 .pSetLayouts = &device->meta_state.query.ds_layout,
800 radv_CreatePipelineLayout(radv_device_to_handle(device), &occlusion_pl_create_info,
801 &device->meta_state.alloc, &device->meta_state.query.p_layout);
817 .layout = device->meta_state.query.p_layout,
821 radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
822 &occlusion_vk_pipeline_info, NULL, &device->meta_state.query.occlusion_query_pipeline);
838 .layout = device->meta_state.query.p_layout,
842 radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
844 &device->meta_state.query.pipeline_statistics_query_pipeline);
860 .layout = device->meta_state.query.p_layout,
864 radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
865 &tfb_pipeline_info, NULL, &device->meta_state.query.tfb_query_pipeline);
881 .layout = device->meta_state.query.p_layout,
885 radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
886 ×tamp_pipeline_info, NULL, &device->meta_state.query.timestamp_query_pipeline);
902 .layout = device->meta_state.query.p_layout,
906 radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
907 &pg_pipeline_info, NULL, &device->meta_state.query.pg_query_pipeline);
915 mtx_unlock(&device->meta_state.mtx);
920 radv_device_init_meta_query_state(struct radv_device *device, bool on_demand)
925 return radv_device_init_meta_query_state_internal(device);
929 radv_device_finish_meta_query_state(struct radv_device *device)
931 if (device->meta_state.query.tfb_query_pipeline)
932 radv_DestroyPipeline(radv_device_to_handle(device),
933 device->meta_state.query.tfb_query_pipeline, &device->meta_state.alloc);
935 if (device->meta_state.query.pipeline_statistics_query_pipeline)
936 radv_DestroyPipeline(radv_device_to_handle(device),
937 device->meta_state.query.pipeline_statistics_query_pipeline,
938 &device->meta_state.alloc);
940 if (device->meta_state.query.occlusion_query_pipeline)
941 radv_DestroyPipeline(radv_device_to_handle(device),
942 device->meta_state.query.occlusion_query_pipeline,
943 &device->meta_state.alloc);
945 if (device->meta_state.query.timestamp_query_pipeline)
946 radv_DestroyPipeline(radv_device_to_handle(device),
947 device->meta_state.query.timestamp_query_pipeline,
948 &device->meta_state.alloc);
950 if (device->meta_state.query.pg_query_pipeline)
951 radv_DestroyPipeline(radv_device_to_handle(device),
952 device->meta_state.query.pg_query_pipeline, &device->meta_state.alloc);
954 if (device->meta_state.query.p_layout)
955 radv_DestroyPipelineLayout(radv_device_to_handle(device), device->meta_state.query.p_layout,
956 &device->meta_state.alloc);
958 if (device->meta_state.query.ds_layout)
959 device->vk.dispatch_table.DestroyDescriptorSetLayout(radv_device_to_handle(device),
960 device->meta_state.query.ds_layout,
961 &device->meta_state.alloc);
971 struct radv_device *device = cmd_buffer->device;
976 VkResult ret = radv_device_init_meta_query_state_internal(device);
993 radv_buffer_init(&src_buffer, device, src_bo, src_buffer_size, src_offset);
994 radv_buffer_init(&dst_buffer, device, dst_bo, dst_buffer_size, dst_offset);
1000 cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, device->meta_state.query.p_layout, 0, /* set */
1034 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.query.p_layout,
1058 radv_destroy_query_pool(struct radv_device *device, const VkAllocationCallbacks *pAllocator,
1065 device->ws->buffer_destroy(device->ws, pool->bo);
1067 vk_free2(&device->vk.alloc, pAllocator, pool);
1074 RADV_FROM_HANDLE(radv_device, device, _device);
1080 struct radv_query_pool *pool = vk_alloc2(&device->vk.alloc, pAllocator, pool_struct_size, 8,
1084 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
1086 vk_object_base_init(&device->vk, &pool->base, VK_OBJECT_TYPE_QUERY_POOL);
1095 pool->uses_gds = device->physical_device->use_ngg &&
1101 pool->stride = 16 * device->physical_device->rad_info.max_render_backends;
1130 result = radv_pc_init_query_pool(device->physical_device, pCreateInfo,
1134 radv_destroy_query_pool(device, pAllocator, pool);
1135 return vk_error(device, result);
1148 result = device->ws->buffer_create(device->ws, pool->size, 64, RADEON_DOMAIN_GTT,
1152 radv_destroy_query_pool(device, pAllocator, pool);
1153 return vk_error(device, result);
1156 pool->ptr = device->ws->buffer_map(pool->bo);
1158 radv_destroy_query_pool(device, pAllocator, pool);
1159 return vk_error(device, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1169 RADV_FROM_HANDLE(radv_device, device, _device);
1175 radv_destroy_query_pool(device, pAllocator, pool);
1183 RADV_FROM_HANDLE(radv_device, device, _device);
1188 if (vk_device_is_lost(&device->vk))
1228 uint32_t db_count = device->physical_device->rad_info.max_render_backends;
1229 uint32_t enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
1499 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pool->bo);
1500 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo);
1505 if (cmd_buffer->device->instance->flush_before_query_copy)
1521 unsigned enabled_rb_mask = cmd_buffer->device->physical_device->rad_info.enabled_rb_mask;
1527 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1533 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.occlusion_query_pipeline,
1543 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1552 cmd_buffer, &cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
1567 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1577 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.timestamp_query_pipeline,
1588 radeon_check_space(cmd_buffer->device->ws, cs, 7 * 4);
1598 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.tfb_query_pipeline,
1609 radeon_check_space(cmd_buffer->device->ws, cs, 7 * 2);
1617 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.pg_query_pipeline,
1714 radeon_check_space(cmd_buffer->device->ws, cs, 4);
1749 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1774 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
1776 BITFIELD64_MASK(cmd_buffer->device->physical_device->rad_info.max_render_backends);
1788 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
1798 radeon_check_space(cmd_buffer->device->ws, cs, 4);
1865 radeon_check_space(cmd_buffer->device->ws, cs, 14);
1878 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
1888 radeon_check_space(cmd_buffer->device->ws, cs, 16);
1902 si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
1950 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
1965 radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
2031 radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
2039 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28 * num_queries);
2051 si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
2062 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
2082 radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
2087 radeon_check_space(cmd_buffer->device->ws, cs, 6 * accelerationStructureCount);