Lines Matching defs:cmd_buffer
965 radv_query_shader(struct radv_cmd_buffer *cmd_buffer, VkPipeline *pipeline,
971 struct radv_device *device = cmd_buffer->device;
978 cmd_buffer->record_result = ret;
986 radv_meta_save(&saved_state, cmd_buffer,
996 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
1000 cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, device->meta_state.query.p_layout, 0, /* set */
1034 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.query.p_layout,
1037 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_INV_VCACHE;
1040 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER;
1042 radv_unaligned_dispatch(cmd_buffer, count, 1, 1);
1048 cmd_buffer->active_query_flush_bits |=
1054 radv_meta_restore(&saved_state, cmd_buffer);
1440 emit_query_flush(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool)
1442 if (cmd_buffer->pending_reset_query) {
1449 si_emit_cache_flush(cmd_buffer);
1487 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1490 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1499 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pool->bo);
1500 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo);
1505 if (cmd_buffer->device->instance->flush_before_query_copy)
1506 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
1516 emit_query_flush(cmd_buffer, pool);
1521 unsigned enabled_rb_mask = cmd_buffer->device->physical_device->rad_info.enabled_rb_mask;
1527 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1533 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.occlusion_query_pipeline,
1543 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1552 cmd_buffer, &cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
1567 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1577 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.timestamp_query_pipeline,
1588 radeon_check_space(cmd_buffer->device->ws, cs, 7 * 4);
1598 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.tfb_query_pipeline,
1609 radeon_check_space(cmd_buffer->device->ws, cs, 7 * 2);
1617 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.pg_query_pipeline,
1646 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1655 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
1657 flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo,
1663 radv_fill_buffer(cmd_buffer, NULL, pool->bo,
1670 cmd_buffer->pending_reset_query = true;
1671 cmd_buffer->state.flush_bits |= flush_bits;
1710 emit_sample_streamout(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint32_t index)
1712 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1714 radeon_check_space(cmd_buffer->device->ws, cs, 4);
1725 gfx10_copy_gds_query(struct radv_cmd_buffer *cmd_buffer, uint32_t gds_offset, uint64_t va)
1727 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1730 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_L2;
1731 si_emit_cache_flush(cmd_buffer);
1743 emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, uint64_t va,
1746 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1749 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1751 ++cmd_buffer->state.active_occlusion_queries;
1752 if (cmd_buffer->state.active_occlusion_queries == 1) {
1757 cmd_buffer->state.perfect_occlusion_queries_enabled = true;
1760 radv_set_db_count_control(cmd_buffer, true);
1763 !cmd_buffer->state.perfect_occlusion_queries_enabled) {
1768 cmd_buffer->state.perfect_occlusion_queries_enabled = true;
1770 radv_set_db_count_control(cmd_buffer, true);
1774 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
1776 BITFIELD64_MASK(cmd_buffer->device->physical_device->rad_info.max_render_backends);
1788 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
1798 radeon_check_space(cmd_buffer->device->ws, cs, 4);
1800 ++cmd_buffer->state.active_pipeline_queries;
1801 if (cmd_buffer->state.active_pipeline_queries == 1) {
1802 cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_STOP_PIPELINE_STATS;
1803 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_START_PIPELINE_STATS;
1814 gfx10_copy_gds_query(cmd_buffer, 0, va); /* NGG GS */
1817 cmd_buffer->gds_needed = true;
1819 cmd_buffer->state.active_pipeline_gds_queries++;
1823 emit_sample_streamout(cmd_buffer, va, index);
1826 if (!cmd_buffer->state.prims_gen_query_enabled) {
1827 bool old_streamout_enabled = radv_is_streamout_enabled(cmd_buffer);
1829 cmd_buffer->state.prims_gen_query_enabled = true;
1831 if (old_streamout_enabled != radv_is_streamout_enabled(cmd_buffer)) {
1832 radv_emit_streamout_enable(cmd_buffer);
1836 emit_sample_streamout(cmd_buffer, va, index);
1839 gfx10_copy_gds_query(cmd_buffer, 0, va + 32); /* NGG GS */
1840 gfx10_copy_gds_query(cmd_buffer, 4, va + 48); /* NGG VS/TES */
1843 cmd_buffer->gds_needed = true;
1845 cmd_buffer->state.active_pipeline_gds_queries++;
1850 radv_pc_begin_query(cmd_buffer, (struct radv_pc_query_pool *)pool, va);
1859 emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool, uint64_t va,
1862 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1865 radeon_check_space(cmd_buffer->device->ws, cs, 14);
1867 cmd_buffer->state.active_occlusion_queries--;
1868 if (cmd_buffer->state.active_occlusion_queries == 0) {
1869 radv_set_db_count_control(cmd_buffer, false);
1874 cmd_buffer->state.perfect_occlusion_queries_enabled = false;
1878 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) {
1888 radeon_check_space(cmd_buffer->device->ws, cs, 16);
1890 cmd_buffer->state.active_pipeline_queries--;
1891 if (cmd_buffer->state.active_pipeline_queries == 0) {
1892 cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_START_PIPELINE_STATS;
1893 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_STOP_PIPELINE_STATS;
1902 si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
1903 radv_cmd_buffer_uses_mec(cmd_buffer), V_028A90_BOTTOM_OF_PIPE_TS,
1905 cmd_buffer->gfx9_eop_bug_va);
1910 gfx10_copy_gds_query(cmd_buffer, 0, va); /* NGG GS */
1912 cmd_buffer->state.active_pipeline_gds_queries--;
1916 emit_sample_streamout(cmd_buffer, va + 16, index);
1919 if (cmd_buffer->state.prims_gen_query_enabled) {
1920 bool old_streamout_enabled = radv_is_streamout_enabled(cmd_buffer);
1922 cmd_buffer->state.prims_gen_query_enabled = false;
1924 if (old_streamout_enabled != radv_is_streamout_enabled(cmd_buffer)) {
1925 radv_emit_streamout_enable(cmd_buffer);
1929 emit_sample_streamout(cmd_buffer, va + 16, index);
1932 gfx10_copy_gds_query(cmd_buffer, 0, va + 40); /* NGG GS */
1933 gfx10_copy_gds_query(cmd_buffer, 4, va + 56); /* NGG VS/TES */
1935 cmd_buffer->state.active_pipeline_gds_queries--;
1940 radv_pc_end_query(cmd_buffer, (struct radv_pc_query_pool *)pool, va);
1947 cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1950 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
1951 cmd_buffer->active_query_flush_bits |=
1960 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1962 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1965 radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
1967 emit_query_flush(cmd_buffer, pool);
1971 emit_begin_query(cmd_buffer, pool, va, pool->type, flags, index);
1985 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1994 emit_end_query(cmd_buffer, pool, va, avail_va, pool->type, index);
2004 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2005 for (unsigned i = 1; i < util_bitcount(cmd_buffer->state.subpass->view_mask); i++) {
2008 emit_begin_query(cmd_buffer, pool, va, pool->type, 0, 0);
2009 emit_end_query(cmd_buffer, pool, va, avail_va, pool->type, 0);
2024 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2026 bool mec = radv_cmd_buffer_uses_mec(cmd_buffer);
2027 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2031 radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
2033 emit_query_flush(cmd_buffer, pool);
2036 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)
2037 num_queries = util_bitcount(cmd_buffer->state.subpass->view_mask);
2039 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28 * num_queries);
2051 si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
2054 cmd_buffer->gfx9_eop_bug_va);
2059 cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
2062 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
2063 cmd_buffer->active_query_flush_bits |=
2067 assert(cmd_buffer->cs->cdw <= cdw_max);
2076 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2078 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2082 radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
2084 emit_query_flush(cmd_buffer, pool);
2087 radeon_check_space(cmd_buffer->device->ws, cs, 6 * accelerationStructureCount);
2121 assert(cmd_buffer->cs->cdw <= cdw_max);