Lines Matching defs:intr
442 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
445 switch (intr->intrinsic) {
447 uint32_t size = align(nir_intrinsic_stack_size(intr), 16) + RADV_MAX_HIT_ATTRIB_SIZE;
448 uint32_t ret_idx = call_idx_base + nir_intrinsic_call_idx(intr) + 1;
459 load_sbt_entry(&b_shader, vars, intr->src[0].ssa, SBT_CALLABLE, 0);
462 nir_iadd_imm(&b_shader, intr->src[1].ssa, -size - 16), 1);
468 uint32_t size = align(nir_intrinsic_stack_size(intr), 16) + RADV_MAX_HIT_ATTRIB_SIZE;
469 uint32_t ret_idx = call_idx_base + nir_intrinsic_call_idx(intr) + 1;
483 nir_iadd_imm(&b_shader, intr->src[10].ssa, -size - 16), 1);
488 nir_store_var(&b_shader, vars->accel_struct, intr->src[0].ssa, 0x1);
489 nir_store_var(&b_shader, vars->flags, intr->src[1].ssa, 0x1);
491 nir_iand_imm(&b_shader, intr->src[2].ssa, 0xff), 0x1);
493 nir_iand_imm(&b_shader, intr->src[3].ssa, 0xf), 0x1);
495 nir_iand_imm(&b_shader, intr->src[4].ssa, 0xf), 0x1);
497 nir_iand_imm(&b_shader, intr->src[5].ssa, 0xffff), 0x1);
498 nir_store_var(&b_shader, vars->origin, intr->src[6].ssa, 0x7);
499 nir_store_var(&b_shader, vars->tmin, intr->src[7].ssa, 0x1);
500 nir_store_var(&b_shader, vars->direction, intr->src[8].ssa, 0x7);
501 nir_store_var(&b_shader, vars->tmax, intr->src[9].ssa, 0x1);
505 uint32_t size = align(nir_intrinsic_stack_size(intr), 16) + RADV_MAX_HIT_ATTRIB_SIZE;
522 instr, &intr->src[0],
523 nir_iadd(&b_shader, nir_load_var(&b_shader, vars->stack_ptr), intr->src[0].ssa));
528 instr, &intr->src[1],
529 nir_iadd(&b_shader, nir_load_var(&b_shader, vars->stack_ptr), intr->src[1].ssa));
604 unsigned c = nir_intrinsic_column(intr);
620 unsigned c = nir_intrinsic_column(intr);
693 nir_fge(&b_shader, nir_load_var(&b_shader, vars->tmax), intr->src[0].ssa),
694 nir_fge(&b_shader, intr->src[0].ssa, nir_load_var(&b_shader, vars->tmin))));
697 nir_store_var(&b_shader, vars->tmax, intr->src[0].ssa, 1);
698 nir_store_var(&b_shader, vars->hit_kind, intr->src[1].ssa, 1);
708 nir_ssa_def_rewrite_uses(&intr->dest.ssa, ret);