Lines Matching refs:rad_info
289 MIN2(max_stage_waves, 4 * device->physical_device->rad_info.num_cu *
477 bool use_rbplus = device->physical_device->rad_info.rbplus_allowed;
700 const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
840 if (device->physical_device->rad_info.has_rbplus) {
853 (device->physical_device->rad_info.gfx_level >= GFX11 && blend.blend_enable_4bit))
1081 unsigned num_tile_pipes = pdevice->rad_info.num_tile_pipes;
1143 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pdevice->rad_info.gfx_level >= GFX9) |
1175 S_028BE0_COVERED_CENTROID_IS_CENTER(pdevice->rad_info.gfx_level >= GFX10_3);
1416 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && pdevice->rad_info.gfx_level <= GFX8)
1435 if ((pdevice->rad_info.family == CHIP_TAHITI ||
1436 pdevice->rad_info.family == CHIP_PITCAIRN ||
1437 pdevice->rad_info.family == CHIP_BONAIRE) &&
1441 if (pdevice->rad_info.has_distributed_tess) {
1443 if (pdevice->rad_info.gfx_level <= GFX8)
1461 if (pdevice->rad_info.family == CHIP_TONGA ||
1462 pdevice->rad_info.family == CHIP_FIJI ||
1463 pdevice->rad_info.family == CHIP_POLARIS10 ||
1464 pdevice->rad_info.family == CHIP_POLARIS11 ||
1465 pdevice->rad_info.family == CHIP_POLARIS12 ||
1466 pdevice->rad_info.family == CHIP_VEGAM) {
1474 S_028AA8_MAX_PRIMGRP_IN_WAVE(pdevice->rad_info.gfx_level == GFX8 ? 2 : 0) |
1475 S_030960_EN_INST_OPT_BASIC(pdevice->rad_info.gfx_level >= GFX9) |
1476 S_030960_EN_INST_OPT_ADV(pdevice->rad_info.gfx_level >= GFX9);
1862 si_translate_blend_factor(pdevice->rad_info.gfx_level, att->srcColorBlendFactor);
1864 si_translate_blend_factor(pdevice->rad_info.gfx_level, att->dstColorBlendFactor);
1866 si_translate_blend_factor(pdevice->rad_info.gfx_level, att->srcAlphaBlendFactor);
1868 si_translate_blend_factor(pdevice->rad_info.gfx_level, att->dstAlphaBlendFactor);
2168 if (device->physical_device->rad_info.gfx_level >= GFX10) {
2214 if (pdevice->rad_info.gfx_level >= GFX10_3)
2235 if (pdevice->rad_info.gfx_level >= GFX11) {
2240 if (pdevice->rad_info.has_dedicated_vram) {
2276 if (pdevice->rad_info.gfx_level >= GFX9)
2386 pdevice->rad_info.gfx_level, stages[es_stage].info.wave_size,
2523 const unsigned min_esverts = pdevice->rad_info.gfx_level >= GFX10_3 ? 29 : 24;
2630 if (pdevice->rad_info.gfx_level == GFX10)
2653 if (pdevice->rad_info.gfx_level == GFX10)
2659 if (pdevice->rad_info.gfx_level == GFX10)
2683 if (pdevice->rad_info.gfx_level == GFX10)
2718 unsigned num_se = pdevice->rad_info.max_se;
2724 unsigned gs_vertex_reuse = (pdevice->rad_info.gfx_level >= GFX8 ? 32 : 16) * num_se;
2742 if (pdevice->rad_info.gfx_level <= GFX8)
2981 bool merged_gs = stages[MESA_SHADER_GEOMETRY].nir && pdevice->rad_info.gfx_level >= GFX9;
3178 ac_nir_lower_indirect_derefs(ordered_shaders[i], pdevice->rad_info.gfx_level);
3187 ac_nir_lower_indirect_derefs(ordered_shaders[i - 1], pdevice->rad_info.gfx_level);
3226 if (pdevice->rad_info.gfx_level >= GFX9) {
3294 device->physical_device->rad_info.gfx_level < GFX8;
3297 device->physical_device->rad_info.gfx_level == GFX9;
3345 if (device->physical_device->rad_info.gfx_level < GFX8) {
3349 if (device->physical_device->rad_info.gfx_level >= GFX11) {
3355 if (device->physical_device->rad_info.gfx_level >= GFX10) {
3374 (device->physical_device->rad_info.family == CHIP_NAVI21 ||
3375 device->physical_device->rad_info.family == CHIP_NAVI22 ||
3376 device->physical_device->rad_info.family == CHIP_VANGOGH))
3452 DIV_ROUND_UP(lds_bytes_if_culling_off, pdevice->rad_info.lds_encode_granularity);
3492 assert(device->physical_device->rad_info.gfx_level < GFX11);
3507 assert(device->physical_device->rad_info.gfx_level < GFX11);
3588 if (device->physical_device->rad_info.gfx_level >= GFX9 &&
3606 if (device->physical_device->rad_info.gfx_level >= GFX9 &&
3703 enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
3814 device->physical_device->hs.tess_offchip_block_dw_size, device->physical_device->rad_info.gfx_level,
3815 device->physical_device->rad_info.family);
3819 device->physical_device->rad_info.gfx_level, tess_in_patch_size, tess_out_patch_size,
3850 device->physical_device->rad_info.gfx_level >= GFX9 &&
3871 ac_compute_lshs_workgroup_size(device->physical_device->rad_info.gfx_level, s, num_patches,
3943 enum amd_gfx_level chip = device->physical_device->rad_info.gfx_level;
4014 enum amd_gfx_level chip = device->physical_device->rad_info.gfx_level;
4497 radv_declare_shader_args(device->physical_device->rad_info.gfx_level, pipeline_key, &info,
4542 if (device->physical_device->rad_info.gfx_level >= GFX9 &&
4810 .has_shared2_amd = device->physical_device->rad_info.gfx_level >= GFX7,
4830 if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) {
4854 .allow_fp16 = device->physical_device->rad_info.gfx_level >= GFX9,
4872 NIR_PASS_V(stages[i].nir, radv_nir_lower_abi, device->physical_device->rad_info.gfx_level,
4879 if (device->physical_device->rad_info.gfx_level >= GFX8) {
4888 if (device->physical_device->rad_info.gfx_level >= GFX8)
4892 device->physical_device->rad_info.gfx_level >= GFX9) {
4893 bool separate_g16 = device->physical_device->rad_info.gfx_level >= GFX10;
5296 util_logbase2_ceil(pdevice->rad_info.max_render_backends / pdevice->rad_info.max_se);
5297 unsigned log_num_se = util_logbase2_ceil(pdevice->rad_info.max_se);
5356 const unsigned rb_count = pdevice->rad_info.max_render_backends;
5357 const unsigned pipe_count = MAX2(rb_count, pdevice->rad_info.num_tcc_blocks);
5435 if (pdevice->rad_info.gfx_level >= GFX10) {
5464 if (pdev->rad_info.has_dedicated_vram) {
5465 if (pdev->rad_info.max_render_backends > 4) {
5481 if (pdev->rad_info.has_gfx9_scissor_bug)
5494 if (device->physical_device->rad_info.gfx_level < GFX9)
5498 if (device->physical_device->rad_info.gfx_level >= GFX10) {
5500 } else if (device->physical_device->rad_info.gfx_level == GFX9) {
5545 if (pdevice->rad_info.has_rbplus) {
5565 if (pdevice->rad_info.gfx_level >= GFX9) {
5612 bool exclusion = pdevice->rad_info.gfx_level >= GFX7;
5636 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out, pdevice->rad_info.gfx_level);
5673 if (pdevice->rad_info.gfx_level >= GFX10) {
5700 if (pdevice->rad_info.gfx_level <= GFX8)
5704 ac_compute_late_alloc(&pdevice->rad_info, false, false, shader->config.scratch_bytes_per_wave > 0,
5707 if (pdevice->rad_info.gfx_level >= GFX7) {
5708 if (pdevice->rad_info.gfx_level >= GFX10) {
5711 C_00B118_CU_EN, 0, &pdevice->rad_info,
5719 if (pdevice->rad_info.gfx_level >= GFX10) {
5720 uint32_t oversub_pc_lines = late_alloc_wave64 ? pdevice->rad_info.pc_lines / 4 : 0;
5721 gfx10_emit_ge_pc_alloc(cs, pdevice->rad_info.gfx_level, oversub_pc_lines);
5750 if (pdevice->rad_info.gfx_level == GFX7 && pdevice->rad_info.family != CHIP_HAWAII)
5845 if (pdevice->rad_info.gfx_level < GFX11) {
5863 if (pdevice->rad_info.gfx_level >= GFX11) {
5883 if (pdevice->rad_info.gfx_level == GFX10 &&
5895 ac_compute_late_alloc(&pdevice->rad_info, true, shader->info.has_ngg_culling,
5898 if (pdevice->rad_info.gfx_level >= GFX11) {
5905 } else if (pdevice->rad_info.gfx_level >= GFX10) {
5908 C_00B21C_CU_EN, 0, &pdevice->rad_info, (void*)gfx10_set_sh_reg_idx3);
5911 C_00B204_CU_EN_GFX10, 16, &pdevice->rad_info,
5922 uint32_t oversub_pc_lines = late_alloc_wave64 ? pdevice->rad_info.pc_lines / 4 : 0;
5934 gfx10_emit_ge_pc_alloc(cs, pdevice->rad_info.gfx_level, oversub_pc_lines);
5944 if (pdevice->rad_info.gfx_level >= GFX9) {
5945 if (pdevice->rad_info.gfx_level >= GFX10) {
6005 if (pdevice->rad_info.gfx_level >= GFX10 &&
6032 if (pdevice->rad_info.gfx_level >= GFX7) {
6079 if (pdevice->rad_info.has_distributed_tess) {
6080 if (pdevice->rad_info.family == CHIP_FIJI || pdevice->rad_info.family >= CHIP_POLARIS10)
6139 if (pdevice->rad_info.gfx_level >= GFX9) {
6140 if (pdevice->rad_info.gfx_level >= GFX10) {
6161 if (pdevice->rad_info.gfx_level >= GFX10) {
6164 C_00B21C_CU_EN, 0, &pdevice->rad_info,
6168 C_00B204_CU_EN_GFX10, 16, &pdevice->rad_info,
6170 } else if (pdevice->rad_info.gfx_level >= GFX7) {
6175 if (pdevice->rad_info.gfx_level >= GFX10) {
6365 bool disable_rbplus = pdevice->rad_info.has_rbplus && !pdevice->rad_info.rbplus_allowed;
6412 param_gen = pdevice->rad_info.gfx_level >= GFX11 &&
6436 if (pdevice->rad_info.family < CHIP_POLARIS10 || pdevice->rad_info.gfx_level >= GFX10)
6482 if (pdevice->rad_info.family >= CHIP_NAVI23)
6489 if (pdevice->rad_info.gfx_level >= GFX9)
6492 if (pdevice->rad_info.gfx_level >= GFX10) {
6592 if (pdevice->rad_info.gfx_level >= GFX11) {
6671 if (pdevice->rad_info.gfx_level >= GFX11) {
6720 if (pdevice->rad_info.gfx_level >= GFX10 && !radv_pipeline_has_ngg(pipeline))
6723 if (pdevice->rad_info.gfx_level >= GFX10_3) {
6806 pipeline, i, device->physical_device->rad_info.gfx_level);
6973 if (device->physical_device->rad_info.gfx_level >= GFX10_3)
6992 if ((device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard) &&
7178 if (pdevice->rad_info.gfx_level >= GFX10) {
7197 if (pdevice->rad_info.gfx_level >= GFX10 && waves_per_threadgroup == 1)
7202 ac_get_compute_resource_limits(&pdevice->rad_info, waves_per_threadgroup,
7218 cs->max_dw = pdevice->rad_info.gfx_level >= GFX10 ? 19 : 16;
7297 if (device->physical_device->rad_info.has_cs_regalloc_hang_bug) {
7506 unsigned lds_increment = pdevice->rad_info.gfx_level >= GFX11 && stage == MESA_SHADER_FRAGMENT
7507 ? 1024 : pdevice->rad_info.lds_encode_granularity;