Lines Matching refs:ps_offset
6246 unsigned slot, uint32_t *ps_input_cntl, unsigned *ps_offset,
6260 ps_input_cntl[*ps_offset] = offset_to_ps_input(vs_offset, flat_shade, false, false);
6261 ++(*ps_offset);
6266 uint32_t input_mask, uint32_t *ps_input_cntl, unsigned *ps_offset)
6271 ps_input_cntl[*ps_offset] = S_028644_OFFSET(0x20);
6272 ++(*ps_offset);
6276 bool flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << *ps_offset));
6277 bool explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << *ps_offset));
6278 bool float16 = !!(ps->info.ps.float16_shaded_mask & (1u << *ps_offset));
6280 ps_input_cntl[*ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
6281 ++(*ps_offset);
6294 unsigned ps_offset = 0;
6297 single_slot_to_ps_input(outinfo, VARYING_SLOT_PRIMITIVE_ID, ps_input_cntl, &ps_offset,
6301 single_slot_to_ps_input(outinfo, VARYING_SLOT_LAYER, ps_input_cntl, &ps_offset,
6305 single_slot_to_ps_input(outinfo, VARYING_SLOT_VIEWPORT, ps_input_cntl, &ps_offset,
6309 ps_input_cntl[ps_offset++] = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
6312 single_slot_to_ps_input(outinfo, VARYING_SLOT_CLIP_DIST0, ps_input_cntl, &ps_offset,
6316 single_slot_to_ps_input(outinfo, VARYING_SLOT_CLIP_DIST1, ps_input_cntl, &ps_offset,
6321 ps_input_cntl, &ps_offset);
6326 single_slot_to_ps_input(outinfo, VARYING_SLOT_PRIMITIVE_ID, ps_input_cntl, &ps_offset,
6330 single_slot_to_ps_input(outinfo, VARYING_SLOT_LAYER, ps_input_cntl, &ps_offset,
6334 single_slot_to_ps_input(outinfo, VARYING_SLOT_VIEWPORT, ps_input_cntl, &ps_offset,
6338 ps_input_cntl, &ps_offset);
6340 if (ps_offset) {
6341 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
6342 for (unsigned i = 0; i < ps_offset; i++) {