Lines Matching refs:pipeline
93 radv_is_raster_enabled(const struct radv_graphics_pipeline *pipeline,
97 (pipeline->dynamic_states & RADV_DYNAMIC_RASTERIZER_DISCARD_ENABLE);
101 radv_is_static_vrs_enabled(const struct radv_graphics_pipeline *pipeline,
110 radv_is_vrs_enabled(const struct radv_graphics_pipeline *pipeline,
113 return radv_is_static_vrs_enabled(pipeline, info) ||
114 (pipeline->dynamic_states & RADV_DYNAMIC_FRAGMENT_SHADING_RATE);
136 radv_pipeline_has_ngg(const struct radv_graphics_pipeline *pipeline)
138 struct radv_shader *shader = pipeline->base.shaders[pipeline->last_vgt_api_stage];
144 radv_pipeline_has_ngg_passthrough(const struct radv_graphics_pipeline *pipeline)
146 assert(radv_pipeline_has_ngg(pipeline));
148 struct radv_shader *shader = pipeline->base.shaders[pipeline->last_vgt_api_stage];
154 radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
156 return !!pipeline->gs_copy_shader;
160 radv_pipeline_slab_create(struct radv_device *device, struct radv_pipeline *pipeline,
171 slab->alloc = radv_alloc_shader_memory(device, code_size, pipeline);
191 radv_pipeline_destroy(struct radv_device *device, struct radv_pipeline *pipeline,
194 if (pipeline->type == RADV_PIPELINE_COMPUTE) {
195 struct radv_compute_pipeline *compute_pipeline = radv_pipeline_to_compute(pipeline);
199 } else if (pipeline->type == RADV_PIPELINE_LIBRARY) {
200 struct radv_library_pipeline *library_pipeline = radv_pipeline_to_library(pipeline);
215 if (pipeline->slab)
216 radv_pipeline_slab_destroy(device, pipeline->slab);
219 if (pipeline->shaders[i])
220 radv_shader_destroy(device, pipeline->shaders[i]);
222 if (pipeline->gs_copy_shader)
223 radv_shader_destroy(device, pipeline->gs_copy_shader);
225 if (pipeline->cs.buf)
226 free(pipeline->cs.buf);
228 vk_object_base_finish(&pipeline->base);
229 vk_free2(&device->vk.alloc, allocator, pipeline);
237 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
242 radv_pipeline_destroy(device, pipeline, pAllocator);
276 radv_pipeline_init_scratch(const struct radv_device *device, struct radv_pipeline *pipeline)
282 if (pipeline->shaders[i] && pipeline->shaders[i]->config.scratch_bytes_per_wave) {
286 MAX2(scratch_bytes_per_wave, pipeline->shaders[i]->config.scratch_bytes_per_wave);
290 radv_get_max_waves(device, pipeline->shaders[i], i));
295 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
296 pipeline->max_waves = max_waves;
532 radv_pipeline_compute_spi_color_formats(const struct radv_graphics_pipeline *pipeline,
549 cf = radv_choose_spi_color_format(pipeline->base.device, fmt, blend_enable,
693 radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline,
697 const struct radv_device *device = pipeline->base.device;
862 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend, info);
864 pipeline->cb_color_control = cb_color_control;
969 radv_pipeline_has_dynamic_ds_states(const struct radv_graphics_pipeline *pipeline)
971 return !!(pipeline->dynamic_states & (RADV_DYNAMIC_DEPTH_TEST_ENABLE |
980 radv_pipeline_out_of_order_rast(struct radv_graphics_pipeline *pipeline,
986 if (!pipeline->base.device->physical_device->out_of_order_rast_allowed)
997 if (radv_pipeline_has_dynamic_ds_states(pipeline))
1005 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
1050 pipeline->disable_out_of_order_rast_for_occlusion = !dsa_order_invariant.pass_set;
1074 radv_pipeline_init_multisample_state(struct radv_graphics_pipeline *pipeline,
1079 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1080 struct radv_multisample_state *ms = &pipeline->ms;
1090 * "Sample shading is enabled for a graphics pipeline:
1093 * graphics pipeline includes an input variable decorated
1098 * when creating the graphics pipeline is set to VK_TRUE. In
1104 if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.uses_sample_shading) {
1119 out_of_order_rast = radv_pipeline_out_of_order_rast(pipeline, blend, info);
1178 pipeline->spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1186 gfx103_pipeline_init_vrs_state(struct radv_graphics_pipeline *pipeline,
1189 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
1190 struct radv_multisample_state *ms = &pipeline->ms;
1191 struct radv_vrs_state *vrs = &pipeline->vrs;
1326 radv_pipeline_is_blend_enabled(const struct radv_graphics_pipeline *pipeline,
1338 radv_pipeline_needed_dynamic_state(const struct radv_graphics_pipeline *pipeline,
1343 (pipeline->dynamic_states & RADV_DYNAMIC_RASTERIZER_DISCARD_ENABLE);
1347 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH)) {
1367 !(pipeline->dynamic_states & RADV_DYNAMIC_DEPTH_BIAS_ENABLE))
1371 !(pipeline->dynamic_states & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE))
1375 !(pipeline->dynamic_states & RADV_DYNAMIC_STENCIL_TEST_ENABLE))
1388 if (!radv_is_vrs_enabled(pipeline, info))
1391 if (!has_color_att || !radv_pipeline_is_blend_enabled(pipeline, &info->cb))
1401 radv_compute_ia_multi_vgt_param_helpers(struct radv_graphics_pipeline *pipeline)
1403 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1406 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL))
1408 pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
1409 else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
1416 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && pdevice->rad_info.gfx_level <= GFX8)
1421 if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
1423 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
1425 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) {
1427 if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
1428 radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
1433 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) {
1438 radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
1442 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
1451 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
1453 * pipeline uses a GS and partial_vs_wave is not set.
1495 radv_pipeline_init_vertex_input_info(struct radv_graphics_pipeline *pipeline,
1498 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1502 if (!(pipeline->dynamic_states & RADV_DYNAMIC_VERTEX_INPUT)) {
1560 if (!(pipeline->dynamic_states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE)) {
1563 * "If the bound pipeline state object was created
1570 * state from the pipeline state object is ignored."
1595 radv_pipeline_init_input_assembly_info(struct radv_graphics_pipeline *pipeline,
1608 radv_pipeline_init_tessellation_info(struct radv_graphics_pipeline *pipeline,
1616 if ((pipeline->active_stages & tess_stages) == tess_stages) {
1630 radv_pipeline_init_viewport_info(struct radv_graphics_pipeline *pipeline,
1636 if (radv_is_raster_enabled(pipeline, pCreateInfo)) {
1637 if (!(pipeline->dynamic_states & RADV_DYNAMIC_VIEWPORT)) {
1642 if (!(pipeline->dynamic_states & RADV_DYNAMIC_SCISSOR)) {
1658 radv_pipeline_init_rasterization_info(struct radv_graphics_pipeline *pipeline,
1714 radv_pipeline_init_discard_rectangle_info(struct radv_graphics_pipeline *pipeline,
1723 if (!(pipeline->dynamic_states & RADV_DYNAMIC_DISCARD_RECTANGLE)) {
1734 radv_pipeline_init_multisample_info(struct radv_graphics_pipeline *pipeline,
1740 if (radv_is_raster_enabled(pipeline, pCreateInfo)) {
1779 radv_pipeline_init_depth_stencil_info(struct radv_graphics_pipeline *pipeline,
1787 if (radv_is_raster_enabled(pipeline, pCreateInfo) &&
1817 radv_pipeline_init_rendering_info(struct radv_graphics_pipeline *pipeline,
1836 radv_pipeline_init_color_blend_info(struct radv_graphics_pipeline *pipeline,
1839 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1853 if (radv_is_raster_enabled(pipeline, pCreateInfo) && has_color_att) {
1896 radv_pipeline_init_fragment_shading_rate_info(struct radv_graphics_pipeline *pipeline,
1903 if (shading_rate && !(pipeline->dynamic_states & RADV_DYNAMIC_FRAGMENT_SHADING_RATE)) {
1917 radv_pipeline_init_graphics_info(struct radv_graphics_pipeline *pipeline,
1922 /* Vertex input interface structs have to be ignored if the pipeline includes a mesh shader. */
1923 if (!(pipeline->active_stages & VK_SHADER_STAGE_MESH_BIT_NV)) {
1924 info.vi = radv_pipeline_init_vertex_input_info(pipeline, pCreateInfo);
1925 info.ia = radv_pipeline_init_input_assembly_info(pipeline, pCreateInfo);
1928 info.ts = radv_pipeline_init_tessellation_info(pipeline, pCreateInfo);
1929 info.vp = radv_pipeline_init_viewport_info(pipeline, pCreateInfo);
1930 info.rs = radv_pipeline_init_rasterization_info(pipeline, pCreateInfo);
1931 info.dr = radv_pipeline_init_discard_rectangle_info(pipeline, pCreateInfo);
1933 info.ms = radv_pipeline_init_multisample_info(pipeline, pCreateInfo);
1934 info.ds = radv_pipeline_init_depth_stencil_info(pipeline, pCreateInfo);
1935 info.ri = radv_pipeline_init_rendering_info(pipeline, pCreateInfo);
1936 info.cb = radv_pipeline_init_color_blend_info(pipeline, pCreateInfo);
1938 info.fsr = radv_pipeline_init_fragment_shading_rate_info(pipeline, pCreateInfo);
1956 radv_pipeline_init_input_assembly_state(struct radv_graphics_pipeline *pipeline,
1959 pipeline->ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline);
1963 radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
1966 uint64_t needed_states = radv_pipeline_needed_dynamic_state(pipeline, info);
1969 pipeline->dynamic_state = default_dynamic_state;
1970 pipeline->needed_dynamic_state = needed_states;
1972 states &= ~pipeline->dynamic_states;
1974 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
2005 * pColorBlendState is [...] NULL if the pipeline has rasterization
2006 * disabled or if the subpass of the render pass the pipeline is
2033 * pDepthStencilState is [...] NULL if the pipeline has rasterization
2034 * disabled or if the subpass of the render pass the pipeline is created
2115 pipeline->uses_dynamic_stride = true;
2147 pipeline->dynamic_state.mask = states;
2151 radv_pipeline_init_raster_state(struct radv_graphics_pipeline *pipeline,
2154 const struct radv_device *device = pipeline->base.device;
2156 pipeline->pa_su_sc_mode_cntl =
2170 pipeline->pa_su_sc_mode_cntl |=
2174 pipeline->pa_cl_clip_cntl =
2175 S_028810_DX_CLIP_SPACE_DEF(!pipeline->negative_one_to_one) |
2181 pipeline->uses_conservative_overestimate =
2184 pipeline->depth_clamp_mode = RADV_DEPTH_CLAMP_MODE_VIEWPORT;
2192 pipeline->depth_clamp_mode = RADV_DEPTH_CLAMP_MODE_DISABLED;
2194 pipeline->depth_clamp_mode = RADV_DEPTH_CLAMP_MODE_ZERO_TO_ONE;
2200 radv_pipeline_init_depth_stencil_state(struct radv_graphics_pipeline *pipeline,
2203 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
2232 if (pipeline->depth_clamp_mode == RADV_DEPTH_CLAMP_MODE_DISABLED)
2262 pipeline->db_depth_control = db_depth_control;
2268 gfx9_get_gs_info(const struct radv_pipeline_key *key, const struct radv_pipeline *pipeline,
2271 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
2485 gfx10_get_ngg_info(const struct radv_pipeline_key *key, struct radv_pipeline *pipeline,
2488 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
2715 radv_pipeline_init_gs_ring_state(struct radv_graphics_pipeline *pipeline, const struct gfx9_gs_info *gs)
2717 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
2728 struct radv_shader_info *gs_info = &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info;
2743 pipeline->esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2745 pipeline->gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2749 radv_get_shader(const struct radv_pipeline *pipeline, gl_shader_stage stage)
2752 if (pipeline->shaders[MESA_SHADER_VERTEX])
2753 return pipeline->shaders[MESA_SHADER_VERTEX];
2754 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
2755 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
2756 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2757 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2759 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL])
2761 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
2762 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
2763 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2764 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2766 return pipeline->shaders[stage];
2770 get_vs_output_info(const struct radv_graphics_pipeline *pipeline)
2772 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2773 if (radv_pipeline_has_ngg(pipeline))
2774 return &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2776 return &pipeline->base.gs_copy_shader->info.vs.outinfo;
2777 else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL))
2778 return &pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2779 else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))
2780 return &pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.outinfo;
2782 return &pipeline->base.shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2933 radv_link_shaders(struct radv_pipeline *pipeline,
2939 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
3194 radv_set_driver_locations(struct radv_pipeline *pipeline, struct radv_pipeline_stage *stages,
3197 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
3283 radv_generate_pipeline_key(const struct radv_pipeline *pipeline, VkPipelineCreateFlags flags)
3285 struct radv_device *device = pipeline->device;
3303 radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipeline,
3308 struct radv_device *device = pipeline->base.device;
3309 struct radv_pipeline_key key = radv_generate_pipeline_key(&pipeline->base, pCreateInfo->flags);
3313 if (pipeline->dynamic_states & RADV_DYNAMIC_VERTEX_INPUT) {
3373 if ((radv_is_vrs_enabled(pipeline, info) || device->force_vrs_enabled) &&
3416 radv_determine_ngg_settings(struct radv_pipeline *pipeline,
3421 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
3438 !radv_use_llvm_for_stage(pipeline->device, es_stage);
3465 radv_fill_shader_info_ngg(struct radv_pipeline *pipeline,
3469 struct radv_device *device = pipeline->device;
3515 /* Determine if the pipeline is eligible for the NGG passthrough
3531 radv_fill_shader_info(struct radv_pipeline *pipeline,
3537 struct radv_device *device = pipeline->device;
3808 /* Number of tessellation patches per workgroup processed by the current pipeline. */
4067 radv_upload_shaders(struct radv_device *device, struct radv_pipeline *pipeline,
4074 struct radv_shader *shader = pipeline->shaders[i];
4081 if (pipeline->gs_copy_shader) {
4082 code_size += align(pipeline->gs_copy_shader->code_size, RADV_SHADER_ALLOC_ALIGNMENT);
4086 pipeline->slab = radv_pipeline_slab_create(device, pipeline, code_size);
4087 if (!pipeline->slab)
4090 pipeline->slab_bo = pipeline->slab->alloc->arena->bo;
4093 uint64_t slab_va = radv_buffer_get_va(pipeline->slab_bo);
4094 uint32_t slab_offset = pipeline->slab->alloc->offset;
4095 char *slab_ptr = pipeline->slab->alloc->arena->ptr;
4098 struct radv_shader *shader = pipeline->shaders[i];
4111 if (pipeline->gs_copy_shader) {
4112 pipeline->gs_copy_shader->va = slab_va + slab_offset;
4115 if (!radv_shader_binary_upload(device, gs_copy_binary, pipeline->gs_copy_shader, dest_ptr))
4123 radv_consider_force_vrs(const struct radv_pipeline *pipeline, bool noop_fs,
4127 struct radv_device *device = pipeline->device;
4475 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
4482 struct radv_device *device = pipeline->device;
4508 radv_pipeline_nir_to_asm(struct radv_pipeline *pipeline, struct radv_pipeline_stage *stages,
4516 struct radv_device *device = pipeline->device;
4528 pipeline->gs_copy_shader =
4529 radv_pipeline_create_gs_copy_shader(pipeline, stages, pipeline_key, pipeline_layout,
4535 if (!(active_stages & (1 << s)) || pipeline->shaders[s])
4559 pipeline->shaders[s] = radv_shader_nir_to_asm(device, &stages[s], shaders, shader_count,
4572 radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout *pipeline_layout,
4623 /* Primitive and mesh shading must not be mixed in the same pipeline. */
4637 pipeline->pipeline_hash = *(uint64_t *)hash;
4641 radv_create_shaders_from_pipeline_cache(device, cache, hash, pipeline,
4657 if (pipeline->type == RADV_PIPELINE_GRAPHICS && !stages[MESA_SHADER_FRAGMENT].entrypoint) {
4684 if (radv_consider_force_vrs(pipeline, noop_fs, stages, *last_vgt_api_stage)) {
4695 radv_fill_shader_info_ngg(pipeline, pipeline_key, stages);
4713 radv_link_shaders(pipeline, pipeline_key, stages, optimize_conservatively, *last_vgt_api_stage);
4714 radv_set_driver_locations(pipeline, stages, *last_vgt_api_stage);
4745 radv_fill_shader_info(pipeline, pipeline_layout, pipeline_key, stages, *last_vgt_api_stage);
4764 gfx10_get_ngg_info(pipeline_key, pipeline, stages, ngg_info);
4768 gfx9_get_gs_info(pipeline_key, pipeline, stages, gs_info);
4775 radv_determine_ngg_settings(pipeline, pipeline_key, stages, *last_vgt_api_stage);
4830 if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) {
4945 radv_pipeline_nir_to_asm(pipeline, stages, pipeline_key, pipeline_layout, keep_executable_info,
4950 struct radv_shader *shader = pipeline->shaders[i];
4964 radv_upload_shaders(device, pipeline, binaries, gs_copy_binary);
4967 if (pipeline->gs_copy_shader) {
4968 assert(!binaries[MESA_SHADER_COMPUTE] && !pipeline->shaders[MESA_SHADER_COMPUTE]);
4970 pipeline->shaders[MESA_SHADER_COMPUTE] = pipeline->gs_copy_shader;
4973 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline, binaries,
4977 if (pipeline->gs_copy_shader) {
4978 pipeline->gs_copy_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4979 pipeline->shaders[MESA_SHADER_COMPUTE] = NULL;
4988 if (radv_can_dump_shader_stats(device, stages[i].nir) && pipeline->shaders[i]) {
4989 radv_dump_shader_stats(device, pipeline, i, stderr);
5014 radv_pipeline_stage_to_user_data_0(struct radv_graphics_pipeline *pipeline, gl_shader_stage stage,
5017 bool has_gs = radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY);
5018 bool has_tess = radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL);
5019 bool has_ngg = radv_pipeline_has_ngg(pipeline);
5079 radv_gfx9_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
5082 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5299 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->ms.pa_sc_aa_config);
5300 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->ms.db_eqaa);
5343 radv_gfx10_compute_bin_size(const struct radv_graphics_pipeline *pipeline,
5346 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5366 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->ms.pa_sc_aa_config);
5428 radv_pipeline_init_disabled_binning_state(struct radv_graphics_pipeline *pipeline,
5431 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5457 pipeline->binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
5488 radv_pipeline_init_binning_state(struct radv_graphics_pipeline *pipeline,
5492 const struct radv_device *device = pipeline->base.device;
5499 bin_size = radv_gfx10_compute_bin_size(pipeline, info);
5501 bin_size = radv_gfx9_compute_bin_size(pipeline, info);
5518 pipeline->binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
5520 radv_pipeline_init_disabled_binning_state(pipeline, info);
5536 const struct radv_graphics_pipeline *pipeline,
5539 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5558 const struct radv_graphics_pipeline *pipeline,
5561 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5592 const struct radv_graphics_pipeline *pipeline)
5594 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5595 const struct radv_multisample_state *ms = &pipeline->ms;
5620 const struct radv_graphics_pipeline *pipeline)
5622 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5623 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
5624 const struct radv_shader *vs = pipeline->base.shaders[MESA_SHADER_TESS_EVAL]
5625 ? pipeline->base.shaders[MESA_SHADER_TESS_EVAL]
5626 : pipeline->base.shaders[MESA_SHADER_VERTEX];
5630 if (radv_pipeline_has_ngg(pipeline))
5633 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
5634 const struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
5648 const struct radv_graphics_pipeline *pipeline, const struct radv_shader *shader)
5650 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5659 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
5726 radv_pipeline_emit_hw_es(struct radeon_cmdbuf *cs, const struct radv_graphics_pipeline *pipeline,
5739 radv_pipeline_emit_hw_ls(struct radeon_cmdbuf *cs, const struct radv_graphics_pipeline *pipeline,
5742 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5743 unsigned num_lds_blocks = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks;
5760 const struct radv_graphics_pipeline *pipeline,
5763 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5766 radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH) ? MESA_SHADER_MESH :
5767 radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
5768 struct radv_shader *es = pipeline->base.shaders[es_type];
5777 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
5790 struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
5842 struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
5884 !radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL) && ngg_state->hw_max_esverts != 256) {
5938 radv_pipeline_emit_hw_hs(struct radeon_cmdbuf *cs, const struct radv_graphics_pipeline *pipeline,
5941 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5965 const struct radv_graphics_pipeline *pipeline)
5970 vs = pipeline->base.shaders[MESA_SHADER_VERTEX];
5975 radv_pipeline_emit_hw_ls(cs, pipeline, vs);
5977 radv_pipeline_emit_hw_es(cs, pipeline, vs);
5979 radv_pipeline_emit_hw_ngg(ctx_cs, cs, pipeline, vs);
5981 radv_pipeline_emit_hw_vs(ctx_cs, cs, pipeline, vs);
5986 const struct radv_graphics_pipeline *pipeline)
5988 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5991 tcs = pipeline->base.shaders[MESA_SHADER_TESS_CTRL];
5992 tes = pipeline->base.shaders[MESA_SHADER_TESS_EVAL];
5996 radv_pipeline_emit_hw_ngg(ctx_cs, cs, pipeline, tes);
5998 radv_pipeline_emit_hw_es(cs, pipeline, tes);
6000 radv_pipeline_emit_hw_vs(ctx_cs, cs, pipeline, tes);
6003 radv_pipeline_emit_hw_hs(cs, pipeline, tcs);
6006 !radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && !radv_pipeline_has_ngg(pipeline)) {
6015 const struct radv_graphics_pipeline *pipeline,
6018 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6019 struct radv_shader *tes = radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL);
6026 pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; // TCS VERTICES OUT
6027 num_patches = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
6095 const struct radv_graphics_pipeline *pipeline, const struct radv_shader *gs)
6097 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6182 radv_pipeline_emit_hw_vs(ctx_cs, cs, pipeline, pipeline->base.gs_copy_shader);
6187 const struct radv_graphics_pipeline *pipeline)
6191 gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
6196 radv_pipeline_emit_hw_ngg(ctx_cs, cs, pipeline, gs);
6198 radv_pipeline_emit_hw_gs(ctx_cs, cs, pipeline, gs);
6205 const struct radv_graphics_pipeline *pipeline)
6207 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6208 struct radv_shader *ms = pipeline->base.shaders[MESA_SHADER_MESH];
6212 radv_pipeline_emit_hw_ngg(ctx_cs, cs, pipeline, ms);
6287 const struct radv_graphics_pipeline *pipeline)
6289 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6290 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
6291 bool mesh = radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH);
6350 const struct radv_graphics_pipeline *pipeline,
6387 const struct radv_graphics_pipeline *pipeline)
6389 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6393 assert(pipeline->base.shaders[MESA_SHADER_FRAGMENT]);
6395 ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6405 radv_compute_db_shader_control(pdevice, pipeline, ps));
6422 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->spi_baryc_cntl);
6432 const struct radv_graphics_pipeline *pipeline)
6434 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6440 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL) &&
6441 radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.tes.spacing ==
6451 const struct radv_graphics_pipeline *pipeline)
6453 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6455 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) {
6458 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
6460 else if (radv_pipeline_has_ngg(pipeline))
6464 } else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
6466 } else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH)) {
6467 assert(!radv_pipeline_has_ngg_passthrough(pipeline));
6470 if (pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.needs_ms_scratch_ring)
6472 } else if (radv_pipeline_has_ngg(pipeline)) {
6476 if (radv_pipeline_has_ngg(pipeline)) {
6478 if (pipeline->streamout_shader)
6480 if (radv_pipeline_has_ngg_passthrough(pipeline)) {
6485 } else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
6495 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL))
6496 hs_size = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
6498 if (pipeline->base.shaders[MESA_SHADER_GEOMETRY]) {
6499 vs_size = gs_size = pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
6500 if (radv_pipeline_has_gs_copy_shader(&pipeline->base))
6501 vs_size = pipeline->base.gs_copy_shader->info.wave_size;
6502 } else if (pipeline->base.shaders[MESA_SHADER_TESS_EVAL])
6503 vs_size = pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
6504 else if (pipeline->base.shaders[MESA_SHADER_VERTEX])
6505 vs_size = pipeline->base.shaders[MESA_SHADER_VERTEX]->info.wave_size;
6506 else if (pipeline->base.shaders[MESA_SHADER_MESH])
6507 vs_size = gs_size = pipeline->base.shaders[MESA_SHADER_MESH]->info.wave_size;
6509 if (radv_pipeline_has_ngg(pipeline)) {
6510 assert(!radv_pipeline_has_gs_copy_shader(&pipeline->base));
6555 const struct radv_graphics_pipeline *pipeline)
6561 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) {
6562 primgroup_size = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
6563 } else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
6565 &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
6572 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) {
6573 if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
6574 radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
6587 const struct radv_graphics_pipeline *pipeline,
6590 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6601 const struct radv_graphics_pipeline *pipeline,
6604 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
6606 bool enable_vrs = radv_is_vrs_enabled(pipeline, info);
6623 gfx103_pipeline_vrs_coarse_shading(const struct radv_graphics_pipeline *pipeline)
6625 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6626 struct radv_device *device = pipeline->base.device;
6639 const struct radv_graphics_pipeline *pipeline,
6642 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6645 bool enable_vrs = radv_is_vrs_enabled(pipeline, info);
6647 if (!enable_vrs && gfx103_pipeline_vrs_coarse_shading(pipeline)) {
6653 } else if (!radv_is_static_vrs_enabled(pipeline, info) && pipeline->force_vrs_per_vertex &&
6654 get_vs_output_info(pipeline)->writes_primitive_shading_rate) {
6666 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6684 radv_pipeline_emit_pm4(struct radv_graphics_pipeline *pipeline,
6690 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6691 struct radeon_cmdbuf *ctx_cs = &pipeline->base.ctx_cs;
6692 struct radeon_cmdbuf *cs = &pipeline->base.cs;
6700 radv_pipeline_emit_blend_state(ctx_cs, pipeline, blend);
6701 radv_pipeline_emit_raster_state(ctx_cs, pipeline, info);
6702 radv_pipeline_emit_multisample_state(ctx_cs, pipeline);
6703 radv_pipeline_emit_vgt_gs_mode(ctx_cs, pipeline);
6704 radv_pipeline_emit_vertex_shader(ctx_cs, cs, pipeline);
6705 radv_pipeline_emit_mesh_shader(ctx_cs, cs, pipeline);
6707 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) {
6708 radv_pipeline_emit_tess_shaders(ctx_cs, cs, pipeline);
6709 radv_pipeline_emit_tess_state(ctx_cs, pipeline, info);
6712 radv_pipeline_emit_geometry_shader(ctx_cs, cs, pipeline);
6713 radv_pipeline_emit_fragment_shader(ctx_cs, cs, pipeline);
6714 radv_pipeline_emit_ps_inputs(ctx_cs, pipeline);
6715 radv_pipeline_emit_vgt_vertex_reuse(ctx_cs, pipeline);
6716 radv_pipeline_emit_vgt_shader_config(ctx_cs, pipeline);
6718 radv_pipeline_emit_vgt_gs_out(ctx_cs, pipeline, vgt_gs_out_prim_type);
6720 if (pdevice->rad_info.gfx_level >= GFX10 && !radv_pipeline_has_ngg(pipeline))
6721 gfx10_pipeline_emit_ge_cntl(ctx_cs, pipeline);
6724 gfx103_pipeline_emit_vgt_draw_payload_cntl(ctx_cs, pipeline, info);
6725 gfx103_pipeline_emit_vrs_state(ctx_cs, pipeline, info);
6728 pipeline->base.ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
6735 radv_pipeline_init_vertex_input_state(struct radv_graphics_pipeline *pipeline,
6738 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6739 const struct radv_shader_info *vs_info = &radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX)->info;
6742 pipeline->attrib_ends[i] = info->vi.attrib_ends[i];
6743 pipeline->attrib_index_offset[i] = info->vi.attrib_index_offset[i];
6744 pipeline->attrib_bindings[i] = info->vi.attrib_bindings[i];
6748 pipeline->binding_stride[i] = info->vi.binding_stride[i];
6751 pipeline->use_per_attribute_vb_descs = vs_info->vs.use_per_attribute_vb_descs;
6752 pipeline->last_vertex_attrib_bit = util_last_bit(vs_info->vs.vb_desc_usage_mask);
6753 if (pipeline->base.shaders[MESA_SHADER_VERTEX])
6754 pipeline->next_vertex_stage = MESA_SHADER_VERTEX;
6755 else if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL])
6756 pipeline->next_vertex_stage = MESA_SHADER_TESS_CTRL;
6758 pipeline->next_vertex_stage = MESA_SHADER_GEOMETRY;
6759 if (pipeline->next_vertex_stage == MESA_SHADER_VERTEX) {
6760 const struct radv_shader *vs_shader = pipeline->base.shaders[MESA_SHADER_VERTEX];
6761 pipeline->can_use_simple_input = vs_shader->info.is_ngg == pdevice->use_ngg &&
6764 pipeline->can_use_simple_input = false;
6767 pipeline->vb_desc_usage_mask = BITFIELD_MASK(pipeline->last_vertex_attrib_bit);
6769 pipeline->vb_desc_usage_mask = vs_info->vs.vb_desc_usage_mask;
6770 pipeline->vb_desc_alloc_size = util_bitcount(pipeline->vb_desc_usage_mask) * 16;
6774 radv_pipeline_get_streamout_shader(struct radv_graphics_pipeline *pipeline)
6779 struct radv_shader *shader = radv_get_shader(&pipeline->base, i);
6789 radv_shader_need_indirect_descriptor_sets(struct radv_pipeline *pipeline, gl_shader_stage stage)
6792 radv_lookup_user_sgpr(pipeline, stage, AC_UD_INDIRECT_DESCRIPTOR_SETS);
6797 radv_pipeline_init_shader_stages_state(struct radv_graphics_pipeline *pipeline)
6799 struct radv_device *device = pipeline->base.device;
6802 bool shader_exists = !!pipeline->base.shaders[i];
6805 pipeline->base.user_data_0[i] = radv_pipeline_stage_to_user_data_0(
6806 pipeline, i, device->physical_device->rad_info.gfx_level);
6809 pipeline->base.need_indirect_descriptor_sets |=
6810 radv_shader_need_indirect_descriptor_sets(&pipeline->base, i);
6815 radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH) ? MESA_SHADER_MESH : MESA_SHADER_VERTEX;
6818 radv_lookup_user_sgpr(&pipeline->base, first_stage, AC_UD_VS_BASE_VERTEX_START_INSTANCE);
6820 pipeline->vtx_base_sgpr = pipeline->base.user_data_0[first_stage];
6821 pipeline->vtx_base_sgpr += loc->sgpr_idx * 4;
6822 pipeline->vtx_emit_num = loc->num_sgprs;
6823 pipeline->uses_drawid =
6824 radv_get_shader(&pipeline->base, first_stage)->info.vs.needs_draw_id;
6825 pipeline->uses_baseinstance =
6826 radv_get_shader(&pipeline->base, first_stage)->info.vs.needs_base_instance;
6828 assert(first_stage != MESA_SHADER_MESH || !pipeline->uses_baseinstance);
6833 radv_pipeline_init_vgt_gs_out(struct radv_graphics_pipeline *pipeline,
6838 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
6840 si_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
6841 } else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) {
6842 if (pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) {
6846 pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes._primitive_mode);
6848 } else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH)) {
6850 si_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.output_prim);
6859 radv_pipeline_init_extra(struct radv_graphics_pipeline *pipeline,
6877 pipeline->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
6879 pipeline->cb_color_control &= C_028808_MODE;
6880 pipeline->cb_color_control |= S_028808_MODE(extra->custom_blend_mode);
6884 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
6888 if (radv_pipeline_has_ngg(pipeline))
6891 pipeline->rast_prim = *vgt_gs_out_prim_type;
6904 radv_pipeline_init(struct radv_device *device, struct radv_pipeline *pipeline,
6907 vk_object_base_init(&device->vk, &pipeline->base, VK_OBJECT_TYPE_PIPELINE);
6909 pipeline->device = device;
6910 pipeline->type = type;
6914 radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv_device *device,
6922 pipeline->last_vgt_api_stage = MESA_SHADER_NONE;
6924 /* Mark all states declared dynamic at pipeline creation. */
6928 pipeline->dynamic_states |=
6933 /* Mark all active stages at pipeline creation. */
6937 pipeline->active_stages |= sinfo->stage;
6940 struct radv_graphics_pipeline_info info = radv_pipeline_init_graphics_info(pipeline, pCreateInfo);
6942 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, &info);
6948 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &info, &blend);
6950 result = radv_create_shaders(&pipeline->base, pipeline_layout, device, cache, &key, pCreateInfo->pStages,
6952 creation_feedback, NULL, NULL, &pipeline->last_vgt_api_stage);
6956 pipeline->spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
6958 uint32_t vgt_gs_out_prim_type = radv_pipeline_init_vgt_gs_out(pipeline, &info);
6960 radv_pipeline_init_multisample_state(pipeline, &blend, &info, vgt_gs_out_prim_type);
6962 if (!radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))
6963 radv_pipeline_init_input_assembly_state(pipeline, &info);
6964 radv_pipeline_init_dynamic_state(pipeline, &info);
6966 pipeline->negative_one_to_one = info.vp.negative_one_to_one;
6968 radv_pipeline_init_raster_state(pipeline, &info);
6971 radv_pipeline_init_depth_stencil_state(pipeline, &info);
6974 gfx103_pipeline_init_vrs_state(pipeline, &info);
6991 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6998 pipeline->col_format = blend.spi_shader_col_format;
6999 pipeline->cb_target_mask = blend.cb_target_mask;
7001 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && !radv_pipeline_has_ngg(pipeline)) {
7002 struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
7004 radv_pipeline_init_gs_ring_state(pipeline, &gs->info.gs_ring_info);
7007 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL)) {
7008 pipeline->tess_patch_control_points = info.ts.patch_control_points;
7011 if (!radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))
7012 radv_pipeline_init_vertex_input_state(pipeline, &info);
7014 radv_pipeline_init_binning_state(pipeline, &blend, &info);
7015 radv_pipeline_init_shader_stages_state(pipeline);
7016 radv_pipeline_init_scratch(device, &pipeline->base);
7019 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
7021 pipeline->is_ngg = radv_pipeline_has_ngg(pipeline);
7022 pipeline->has_ngg_culling =
7023 pipeline->is_ngg &&
7024 pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.has_ngg_culling;
7025 pipeline->force_vrs_per_vertex =
7026 pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.force_vrs_per_vertex;
7027 pipeline->uses_user_sample_locations = info.ms.sample_locs_enable;
7028 pipeline->rast_prim = vgt_gs_out_prim_type;
7030 if (!(pipeline->dynamic_states & RADV_DYNAMIC_LINE_WIDTH)) {
7031 pipeline->line_width = info.rs.line_width;
7034 pipeline->base.push_constant_size = pipeline_layout->push_constant_size;
7035 pipeline->base.dynamic_offset_count = pipeline_layout->dynamic_offset_count;
7038 radv_pipeline_init_extra(pipeline, extra, &blend, &ds_state, &info, &vgt_gs_out_prim_type);
7041 radv_pipeline_emit_pm4(pipeline, &blend, &ds_state, vgt_gs_out_prim_type, &info);
7055 struct radv_graphics_pipeline *pipeline;
7058 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
7060 if (pipeline == NULL)
7063 radv_pipeline_init(device, &pipeline->base, RADV_PIPELINE_GRAPHICS);
7065 result = radv_graphics_pipeline_init(pipeline, device, cache, pCreateInfo, extra);
7067 radv_pipeline_destroy(device, &pipeline->base, pAllocator);
7071 *pPipeline = radv_pipeline_to_handle(&pipeline->base);
7212 radv_compute_generate_pm4(struct radv_compute_pipeline *pipeline)
7214 struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
7215 struct radv_shader *shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
7216 struct radeon_cmdbuf *cs = &pipeline->base.cs;
7224 assert(pipeline->base.cs.cdw <= pipeline->base.cs.max_dw);
7228 radv_generate_compute_pipeline_key(struct radv_compute_pipeline *pipeline,
7232 struct radv_pipeline_key key = radv_generate_pipeline_key(&pipeline->base, pCreateInfo->flags);
7259 struct radv_compute_pipeline *pipeline;
7262 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
7264 if (pipeline == NULL) {
7269 radv_pipeline_init(device, &pipeline->base, RADV_PIPELINE_COMPUTE);
7271 pipeline->rt_stack_sizes = rt_stack_sizes;
7272 pipeline->group_count = rt_group_count;
7277 struct radv_pipeline_key key = radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
7280 result = radv_create_shaders(&pipeline->base, pipeline_layout, device, cache, &key, &pCreateInfo->stage,
7282 &pipeline->rt_stack_sizes, &pipeline->group_count,
7285 radv_pipeline_destroy(device, &pipeline->base, pAllocator);
7289 pipeline->base.user_data_0[MESA_SHADER_COMPUTE] = R_00B900_COMPUTE_USER_DATA_0;
7290 pipeline->base.need_indirect_descriptor_sets |=
7291 radv_shader_need_indirect_descriptor_sets(&pipeline->base, MESA_SHADER_COMPUTE);
7292 radv_pipeline_init_scratch(device, &pipeline->base);
7294 pipeline->base.push_constant_size = pipeline_layout->push_constant_size;
7295 pipeline->base.dynamic_offset_count = pipeline_layout->dynamic_offset_count;
7298 struct radv_shader *compute_shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
7301 pipeline->cs_regalloc_hang_bug = cs_block_size[0] * cs_block_size[1] * cs_block_size[2] > 256;
7304 radv_compute_generate_pm4(pipeline);
7306 *pPipeline = radv_pipeline_to_handle(&pipeline->base);
7339 radv_get_executable_count(struct radv_pipeline *pipeline)
7343 if (!pipeline->shaders[i])
7347 !radv_pipeline_has_ngg(radv_pipeline_to_graphics(pipeline))) {
7357 radv_get_shader_from_executable_index(struct radv_pipeline *pipeline, int index,
7361 if (!pipeline->shaders[i])
7365 return pipeline->shaders[i];
7371 !radv_pipeline_has_ngg(radv_pipeline_to_graphics(pipeline))) {
7374 return pipeline->gs_copy_shader;
7400 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
7401 const uint32_t total_count = radv_get_executable_count(pipeline);
7410 if (!pipeline->shaders[i])
7421 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
7435 if (pipeline->shaders[MESA_SHADER_TESS_CTRL] && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
7439 } else if (!pipeline->shaders[MESA_SHADER_TESS_CTRL] && !pipeline->shaders[MESA_SHADER_VERTEX]) {
7466 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
7472 !radv_pipeline_has_ngg(radv_pipeline_to_graphics(pipeline))) {
7473 assert(pipeline->gs_copy_shader);
7499 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
7502 radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
7515 desc_copy(s->name, "Driver pipeline hash");
7516 desc_copy(s->description, "Driver pipeline hash used by RGP");
7518 s->value.u64 = pipeline->pipeline_hash;
7636 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
7639 radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);