Lines Matching refs:pdevice
1079 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1081 unsigned num_tile_pipes = pdevice->rad_info.num_tile_pipes;
1143 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pdevice->rad_info.gfx_level >= GFX9) |
1175 S_028BE0_COVERED_CENTROID_IS_CENTER(pdevice->rad_info.gfx_level >= GFX10_3);
1403 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1416 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && pdevice->rad_info.gfx_level <= GFX8)
1417 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pdevice->gs_table_depth - 3)
1435 if ((pdevice->rad_info.family == CHIP_TAHITI ||
1436 pdevice->rad_info.family == CHIP_PITCAIRN ||
1437 pdevice->rad_info.family == CHIP_BONAIRE) &&
1441 if (pdevice->rad_info.has_distributed_tess) {
1443 if (pdevice->rad_info.gfx_level <= GFX8)
1461 if (pdevice->rad_info.family == CHIP_TONGA ||
1462 pdevice->rad_info.family == CHIP_FIJI ||
1463 pdevice->rad_info.family == CHIP_POLARIS10 ||
1464 pdevice->rad_info.family == CHIP_POLARIS11 ||
1465 pdevice->rad_info.family == CHIP_POLARIS12 ||
1466 pdevice->rad_info.family == CHIP_VEGAM) {
1474 S_028AA8_MAX_PRIMGRP_IN_WAVE(pdevice->rad_info.gfx_level == GFX8 ? 2 : 0) |
1475 S_030960_EN_INST_OPT_BASIC(pdevice->rad_info.gfx_level >= GFX9) |
1476 S_030960_EN_INST_OPT_ADV(pdevice->rad_info.gfx_level >= GFX9);
1498 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1542 radv_translate_vertex_format(pdevice, desc->format, format_desc, &data_format, &num_format,
1839 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1862 si_translate_blend_factor(pdevice->rad_info.gfx_level, att->srcColorBlendFactor);
1864 si_translate_blend_factor(pdevice->rad_info.gfx_level, att->dstColorBlendFactor);
1866 si_translate_blend_factor(pdevice->rad_info.gfx_level, att->srcAlphaBlendFactor);
1868 si_translate_blend_factor(pdevice->rad_info.gfx_level, att->dstAlphaBlendFactor);
2203 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
2214 if (pdevice->rad_info.gfx_level >= GFX10_3)
2235 if (pdevice->rad_info.gfx_level >= GFX11) {
2240 if (pdevice->rad_info.has_dedicated_vram) {
2271 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
2276 if (pdevice->rad_info.gfx_level >= GFX9)
2386 pdevice->rad_info.gfx_level, stages[es_stage].info.wave_size,
2488 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
2523 const unsigned min_esverts = pdevice->rad_info.gfx_level >= GFX10_3 ? 29 : 24;
2630 if (pdevice->rad_info.gfx_level == GFX10)
2653 if (pdevice->rad_info.gfx_level == GFX10)
2659 if (pdevice->rad_info.gfx_level == GFX10)
2683 if (pdevice->rad_info.gfx_level == GFX10)
2717 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
2718 unsigned num_se = pdevice->rad_info.max_se;
2724 unsigned gs_vertex_reuse = (pdevice->rad_info.gfx_level >= GFX8 ? 32 : 16) * num_se;
2742 if (pdevice->rad_info.gfx_level <= GFX8)
2939 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
2981 bool merged_gs = stages[MESA_SHADER_GEOMETRY].nir && pdevice->rad_info.gfx_level >= GFX9;
3178 ac_nir_lower_indirect_derefs(ordered_shaders[i], pdevice->rad_info.gfx_level);
3187 ac_nir_lower_indirect_derefs(ordered_shaders[i - 1], pdevice->rad_info.gfx_level);
3197 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
3226 if (pdevice->rad_info.gfx_level >= GFX9) {
3421 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
3437 pdevice, stages[es_stage].nir, ps_inputs_read, num_vertices_per_prim, &stages[es_stage].info) &&
3452 DIV_ROUND_UP(lds_bytes_if_culling_off, pdevice->rad_info.lds_encode_granularity);
5082 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5296 util_logbase2_ceil(pdevice->rad_info.max_render_backends / pdevice->rad_info.max_se);
5297 unsigned log_num_se = util_logbase2_ceil(pdevice->rad_info.max_se);
5346 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5356 const unsigned rb_count = pdevice->rad_info.max_render_backends;
5357 const unsigned pipe_count = MAX2(rb_count, pdevice->rad_info.num_tcc_blocks);
5431 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5435 if (pdevice->rad_info.gfx_level >= GFX10) {
5539 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5545 if (pdevice->rad_info.has_rbplus) {
5561 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5565 if (pdevice->rad_info.gfx_level >= GFX9) {
5594 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5612 bool exclusion = pdevice->rad_info.gfx_level >= GFX7;
5622 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5636 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out, pdevice->rad_info.gfx_level);
5650 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5673 if (pdevice->rad_info.gfx_level >= GFX10) {
5700 if (pdevice->rad_info.gfx_level <= GFX8)
5704 ac_compute_late_alloc(&pdevice->rad_info, false, false, shader->config.scratch_bytes_per_wave > 0,
5707 if (pdevice->rad_info.gfx_level >= GFX7) {
5708 if (pdevice->rad_info.gfx_level >= GFX10) {
5711 C_00B118_CU_EN, 0, &pdevice->rad_info,
5714 radeon_set_sh_reg_idx(pdevice, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, 3,
5719 if (pdevice->rad_info.gfx_level >= GFX10) {
5720 uint32_t oversub_pc_lines = late_alloc_wave64 ? pdevice->rad_info.pc_lines / 4 : 0;
5721 gfx10_emit_ge_pc_alloc(cs, pdevice->rad_info.gfx_level, oversub_pc_lines);
5742 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5750 if (pdevice->rad_info.gfx_level == GFX7 && pdevice->rad_info.family != CHIP_HAWAII)
5763 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5845 if (pdevice->rad_info.gfx_level < GFX11) {
5863 if (pdevice->rad_info.gfx_level >= GFX11) {
5883 if (pdevice->rad_info.gfx_level == GFX10 &&
5895 ac_compute_late_alloc(&pdevice->rad_info, true, shader->info.has_ngg_culling,
5898 if (pdevice->rad_info.gfx_level >= GFX11) {
5905 } else if (pdevice->rad_info.gfx_level >= GFX10) {
5908 C_00B21C_CU_EN, 0, &pdevice->rad_info, (void*)gfx10_set_sh_reg_idx3);
5911 C_00B204_CU_EN_GFX10, 16, &pdevice->rad_info,
5915 pdevice, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, 3,
5918 pdevice, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, 3,
5922 uint32_t oversub_pc_lines = late_alloc_wave64 ? pdevice->rad_info.pc_lines / 4 : 0;
5934 gfx10_emit_ge_pc_alloc(cs, pdevice->rad_info.gfx_level, oversub_pc_lines);
5941 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5944 if (pdevice->rad_info.gfx_level >= GFX9) {
5945 if (pdevice->rad_info.gfx_level >= GFX10) {
5988 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6005 if (pdevice->rad_info.gfx_level >= GFX10 &&
6018 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6032 if (pdevice->rad_info.gfx_level >= GFX7) {
6079 if (pdevice->rad_info.has_distributed_tess) {
6080 if (pdevice->rad_info.family == CHIP_FIJI || pdevice->rad_info.family >= CHIP_POLARIS10)
6097 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6139 if (pdevice->rad_info.gfx_level >= GFX9) {
6140 if (pdevice->rad_info.gfx_level >= GFX10) {
6161 if (pdevice->rad_info.gfx_level >= GFX10) {
6164 C_00B21C_CU_EN, 0, &pdevice->rad_info,
6168 C_00B204_CU_EN_GFX10, 16, &pdevice->rad_info,
6170 } else if (pdevice->rad_info.gfx_level >= GFX7) {
6172 pdevice, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, 3,
6175 if (pdevice->rad_info.gfx_level >= GFX10) {
6177 pdevice, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, 3,
6207 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6214 radeon_set_uconfig_reg_idx(pdevice, ctx_cs,
6349 radv_compute_db_shader_control(const struct radv_physical_device *pdevice,
6365 bool disable_rbplus = pdevice->rad_info.has_rbplus && !pdevice->rad_info.rbplus_allowed;
6389 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6405 radv_compute_db_shader_control(pdevice, pipeline, ps));
6412 param_gen = pdevice->rad_info.gfx_level >= GFX11 &&
6434 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6436 if (pdevice->rad_info.family < CHIP_POLARIS10 || pdevice->rad_info.gfx_level >= GFX10)
6453 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6482 if (pdevice->rad_info.family >= CHIP_NAVI23)
6489 if (pdevice->rad_info.gfx_level >= GFX9)
6492 if (pdevice->rad_info.gfx_level >= GFX10) {
6590 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6592 if (pdevice->rad_info.gfx_level >= GFX11) {
6642 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6671 if (pdevice->rad_info.gfx_level >= GFX11) {
6690 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6720 if (pdevice->rad_info.gfx_level >= GFX10 && !radv_pipeline_has_ngg(pipeline))
6723 if (pdevice->rad_info.gfx_level >= GFX10_3) {
6738 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6761 pipeline->can_use_simple_input = vs_shader->info.is_ngg == pdevice->use_ngg &&
6762 vs_shader->info.wave_size == pdevice->ge_wave_size;
7168 radv_pipeline_emit_hw_cs(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs,
7178 if (pdevice->rad_info.gfx_level >= GFX10) {
7184 radv_pipeline_emit_compute_state(const struct radv_physical_device *pdevice,
7197 if (pdevice->rad_info.gfx_level >= GFX10 && waves_per_threadgroup == 1)
7202 ac_get_compute_resource_limits(&pdevice->rad_info, waves_per_threadgroup,
7214 struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
7218 cs->max_dw = pdevice->rad_info.gfx_level >= GFX10 ? 19 : 16;
7221 radv_pipeline_emit_hw_cs(pdevice, cs, shader);
7222 radv_pipeline_emit_compute_state(pdevice, cs, shader);
7504 const struct radv_physical_device *pdevice = device->physical_device;
7506 unsigned lds_increment = pdevice->rad_info.gfx_level >= GFX11 && stage == MESA_SHADER_FRAGMENT
7507 ? 1024 : pdevice->rad_info.lds_encode_granularity;