Lines Matching refs:config
282 if (pipeline->shaders[i] && pipeline->shaders[i]->config.scratch_bytes_per_wave) {
286 MAX2(scratch_bytes_per_wave, pipeline->shaders[i]->config.scratch_bytes_per_wave);
5656 radeon_emit(cs, shader->config.rsrc1);
5657 radeon_emit(cs, shader->config.rsrc2);
5704 ac_compute_late_alloc(&pdevice->rad_info, false, false, shader->config.scratch_bytes_per_wave > 0,
5734 radeon_emit(cs, shader->config.rsrc1);
5735 radeon_emit(cs, shader->config.rsrc2);
5745 uint32_t rsrc2 = shader->config.rsrc2;
5754 radeon_emit(cs, shader->config.rsrc1);
5774 radeon_emit(cs, shader->config.rsrc1);
5775 radeon_emit(cs, shader->config.rsrc2);
5896 shader->config.scratch_bytes_per_wave > 0, &late_alloc_wave64, &cu_mask);
5952 radeon_emit(cs, shader->config.rsrc1);
5953 radeon_emit(cs, shader->config.rsrc2);
5958 radeon_emit(cs, shader->config.rsrc1);
5959 radeon_emit(cs, shader->config.rsrc2);
6147 radeon_emit(cs, gs->config.rsrc1);
6148 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
6157 radeon_emit(cs, gs->config.rsrc1);
6158 radeon_emit(cs, gs->config.rsrc2);
6401 radeon_emit(cs, ps->config.rsrc1);
6402 radeon_emit(cs, ps->config.rsrc2);
6408 radeon_emit(ctx_cs, ps->config.spi_ps_input_ena);
6409 radeon_emit(ctx_cs, ps->config.spi_ps_input_addr);
6413 !ps->info.ps.num_interp && ps->config.lds_size;
7176 radeon_emit(cs, shader->config.rsrc1);
7177 radeon_emit(cs, shader->config.rsrc2);
7179 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3);
7526 s->value.u64 = shader->config.num_sgprs;
7534 s->value.u64 = shader->config.num_vgprs;
7542 s->value.u64 = shader->config.spilled_sgprs;
7550 s->value.u64 = shader->config.spilled_vgprs;
7566 s->value.u64 = shader->config.lds_size * lds_increment;
7574 s->value.u64 = shader->config.scratch_bytes_per_wave;