Lines Matching refs:blend
417 * Get rid of DST in the blend factors by commuting the operands:
493 return formats.blend;
534 struct radv_blend_state *blend,
544 if (fmt == VK_FORMAT_UNDEFINED || !(blend->cb_target_mask & (0xfu << (i * 4)))) {
547 bool blend_enable = blend->blend_enable_4bit & (0xfu << (i * 4));
550 blend->need_src_alpha & (1 << i));
563 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
584 if (blend->mrt0_is_dual_src) {
589 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
590 blend->spi_shader_col_format = col_format;
591 blend->col_format_is_int8 = is_int8;
592 blend->col_format_is_int10 = is_int10;
593 blend->col_format_is_float32 = is_float32;
642 radv_blend_check_commutativity(enum amd_gfx_level gfx_level, struct radv_blend_state *blend,
688 blend->commutative_4bit |= chanmask;
698 struct radv_blend_state blend = {0};
710 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
716 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
722 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
723 blend.need_src_alpha |= 0x1;
726 blend.cb_target_mask = 0;
737 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
743 /* Ignore other blend targets if dual-source blending
746 if (blend.mrt0_is_dual_src)
749 blend.cb_target_mask |= (unsigned)info->cb.att[i].color_write_mask << (4 * i);
750 blend.cb_target_enabled_4bit |= 0xfu << (4 * i);
752 blend.cb_blend_control[i] = blend_cntl;
759 blend.mrt0_is_dual_src = true;
771 radv_blend_check_commutativity(gfx_level, &blend, eqRGB, srcRGB, dstRGB, 0x7u << (4 * i));
772 radv_blend_check_commutativity(gfx_level, &blend, eqA, srcA, dstA, 0x8u << (4 * i));
777 * First, get rid of DST in the blend factors:
807 blend.sx_mrt_blend_opt[i] =
823 blend.cb_blend_control[i] = blend_cntl;
825 blend.blend_enable_4bit |= 0xfu << (i * 4);
832 blend.need_src_alpha |= 1 << i;
835 blend.cb_blend_control[i] = 0;
836 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
841 /* Disable RB+ blend optimizations for dual source blending. */
842 if (blend.mrt0_is_dual_src) {
844 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
852 if (blend.mrt0_is_dual_src || info->cb.logic_op_enable ||
853 (device->physical_device->rad_info.gfx_level >= GFX11 && blend.blend_enable_4bit))
857 if (blend.cb_target_mask)
862 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend, info);
866 return blend;
981 const struct radv_blend_state *blend,
984 unsigned colormask = blend->cb_target_enabled_4bit;
1056 unsigned blendmask = colormask & blend->blend_enable_4bit;
1060 if (blendmask & ~blend->commutative_4bit)
1075 const struct radv_blend_state *blend,
1119 out_of_order_rast = radv_pipeline_out_of_order_rast(pipeline, blend, info);
3306 const struct radv_blend_state *blend)
3342 key.ps.col_format = blend->spi_shader_col_format;
3343 key.ps.cb_target_mask = blend->cb_target_mask;
3344 key.ps.mrt0_is_dual_src = blend->mrt0_is_dual_src;
3346 key.ps.is_int8 = blend->col_format_is_int8;
3347 key.ps.is_int10 = blend->col_format_is_int10;
3363 key.ps.enable_mrt_output_nan_fixup = blend->col_format_is_float32;
5489 const struct radv_blend_state *blend,
5537 const struct radv_blend_state *blend)
5542 radeon_emit_array(ctx_cs, blend->cb_blend_control, 8);
5543 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
5548 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
5551 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
5553 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
6685 const struct radv_blend_state *blend,
6700 radv_pipeline_emit_blend_state(ctx_cs, pipeline, blend);
6942 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, &info);
6948 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &info, &blend);
6960 radv_pipeline_init_multisample_state(pipeline, &blend, &info, vgt_gs_out_prim_type);
6993 !blend.spi_shader_col_format) {
6995 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
6998 pipeline->col_format = blend.spi_shader_col_format;
6999 pipeline->cb_target_mask = blend.cb_target_mask;
7014 radv_pipeline_init_binning_state(pipeline, &blend, &info);
7038 radv_pipeline_init_extra(pipeline, extra, &blend, &ds_state, &info, &vgt_gs_out_prim_type);
7041 radv_pipeline_emit_pm4(pipeline, &blend, &ds_state, vgt_gs_out_prim_type, &info);