Lines Matching refs:base
138 struct radv_shader *shader = pipeline->base.shaders[pipeline->last_vgt_api_stage];
148 struct radv_shader *shader = pipeline->base.shaders[pipeline->last_vgt_api_stage];
206 vk_object_base_finish(&module->base);
228 vk_object_base_finish(&pipeline->base);
549 cf = radv_choose_spi_color_format(pipeline->base.device, fmt, blend_enable,
697 const struct radv_device *device = pipeline->base.device;
986 if (!pipeline->base.device->physical_device->out_of_order_rast_allowed)
1005 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
1079 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1104 if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.uses_sample_shading) {
1189 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
1403 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1408 pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
1421 if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
1423 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
1427 if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
1428 radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
1471 ia_multi_vgt_param.base =
1498 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1839 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
2154 const struct radv_device *device = pipeline->base.device;
2203 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
2453 * - base vertex ~ first workgroup index (firstTask in NV_mesh_shader)
2717 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
2728 struct radv_shader_info *gs_info = &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info;
2774 return &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2776 return &pipeline->base.gs_copy_shader->info.vs.outinfo;
2778 return &pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2780 return &pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.outinfo;
2782 return &pipeline->base.shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
3308 struct radv_device *device = pipeline->base.device;
3309 struct radv_pipeline_key key = radv_generate_pipeline_key(&pipeline->base, pCreateInfo->flags);
4462 out_stage->spirv.object = &module->base;
5082 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5346 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5431 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5492 const struct radv_device *device = pipeline->base.device;
5539 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5561 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5594 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5622 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5624 const struct radv_shader *vs = pipeline->base.shaders[MESA_SHADER_TESS_EVAL]
5625 ? pipeline->base.shaders[MESA_SHADER_TESS_EVAL]
5626 : pipeline->base.shaders[MESA_SHADER_VERTEX];
5634 const struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
5650 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5742 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5743 unsigned num_lds_blocks = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks;
5763 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5768 struct radv_shader *es = pipeline->base.shaders[es_type];
5790 struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
5842 struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
5941 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5970 vs = pipeline->base.shaders[MESA_SHADER_VERTEX];
5988 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5991 tcs = pipeline->base.shaders[MESA_SHADER_TESS_CTRL];
5992 tes = pipeline->base.shaders[MESA_SHADER_TESS_EVAL];
6018 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6019 struct radv_shader *tes = radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL);
6026 pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; // TCS VERTICES OUT
6027 num_patches = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
6097 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6182 radv_pipeline_emit_hw_vs(ctx_cs, cs, pipeline, pipeline->base.gs_copy_shader);
6191 gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
6207 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6208 struct radv_shader *ms = pipeline->base.shaders[MESA_SHADER_MESH];
6289 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6389 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6393 assert(pipeline->base.shaders[MESA_SHADER_FRAGMENT]);
6395 ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6434 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6441 radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.tes.spacing ==
6453 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6470 if (pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.needs_ms_scratch_ring)
6496 hs_size = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
6498 if (pipeline->base.shaders[MESA_SHADER_GEOMETRY]) {
6499 vs_size = gs_size = pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
6500 if (radv_pipeline_has_gs_copy_shader(&pipeline->base))
6501 vs_size = pipeline->base.gs_copy_shader->info.wave_size;
6502 } else if (pipeline->base.shaders[MESA_SHADER_TESS_EVAL])
6503 vs_size = pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
6504 else if (pipeline->base.shaders[MESA_SHADER_VERTEX])
6505 vs_size = pipeline->base.shaders[MESA_SHADER_VERTEX]->info.wave_size;
6506 else if (pipeline->base.shaders[MESA_SHADER_MESH])
6507 vs_size = gs_size = pipeline->base.shaders[MESA_SHADER_MESH]->info.wave_size;
6510 assert(!radv_pipeline_has_gs_copy_shader(&pipeline->base));
6562 primgroup_size = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
6565 &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
6573 if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
6574 radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
6590 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6625 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6626 struct radv_device *device = pipeline->base.device;
6642 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6666 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6690 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6691 struct radeon_cmdbuf *ctx_cs = &pipeline->base.ctx_cs;
6692 struct radeon_cmdbuf *cs = &pipeline->base.cs;
6728 pipeline->base.ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
6738 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6739 const struct radv_shader_info *vs_info = &radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX)->info;
6753 if (pipeline->base.shaders[MESA_SHADER_VERTEX])
6755 else if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL])
6760 const struct radv_shader *vs_shader = pipeline->base.shaders[MESA_SHADER_VERTEX];
6779 struct radv_shader *shader = radv_get_shader(&pipeline->base, i);
6799 struct radv_device *device = pipeline->base.device;
6802 bool shader_exists = !!pipeline->base.shaders[i];
6805 pipeline->base.user_data_0[i] = radv_pipeline_stage_to_user_data_0(
6809 pipeline->base.need_indirect_descriptor_sets |=
6810 radv_shader_need_indirect_descriptor_sets(&pipeline->base, i);
6818 radv_lookup_user_sgpr(&pipeline->base, first_stage, AC_UD_VS_BASE_VERTEX_START_INSTANCE);
6820 pipeline->vtx_base_sgpr = pipeline->base.user_data_0[first_stage];
6824 radv_get_shader(&pipeline->base, first_stage)->info.vs.needs_draw_id;
6826 radv_get_shader(&pipeline->base, first_stage)->info.vs.needs_base_instance;
6840 si_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
6842 if (pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) {
6846 pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes._primitive_mode);
6850 si_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.output_prim);
6907 vk_object_base_init(&device->vk, &pipeline->base, VK_OBJECT_TYPE_PIPELINE);
6950 result = radv_create_shaders(&pipeline->base, pipeline_layout, device, cache, &key, pCreateInfo->pStages,
6991 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
7002 struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
7016 radv_pipeline_init_scratch(device, &pipeline->base);
7024 pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.has_ngg_culling;
7026 pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.force_vrs_per_vertex;
7034 pipeline->base.push_constant_size = pipeline_layout->push_constant_size;
7035 pipeline->base.dynamic_offset_count = pipeline_layout->dynamic_offset_count;
7063 radv_pipeline_init(device, &pipeline->base, RADV_PIPELINE_GRAPHICS);
7067 radv_pipeline_destroy(device, &pipeline->base, pAllocator);
7071 *pPipeline = radv_pipeline_to_handle(&pipeline->base);
7214 struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
7215 struct radv_shader *shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
7216 struct radeon_cmdbuf *cs = &pipeline->base.cs;
7224 assert(pipeline->base.cs.cdw <= pipeline->base.cs.max_dw);
7232 struct radv_pipeline_key key = radv_generate_pipeline_key(&pipeline->base, pCreateInfo->flags);
7269 radv_pipeline_init(device, &pipeline->base, RADV_PIPELINE_COMPUTE);
7280 result = radv_create_shaders(&pipeline->base, pipeline_layout, device, cache, &key, &pCreateInfo->stage,
7285 radv_pipeline_destroy(device, &pipeline->base, pAllocator);
7289 pipeline->base.user_data_0[MESA_SHADER_COMPUTE] = R_00B900_COMPUTE_USER_DATA_0;
7290 pipeline->base.need_indirect_descriptor_sets |=
7291 radv_shader_need_indirect_descriptor_sets(&pipeline->base, MESA_SHADER_COMPUTE);
7292 radv_pipeline_init_scratch(device, &pipeline->base);
7294 pipeline->base.push_constant_size = pipeline_layout->push_constant_size;
7295 pipeline->base.dynamic_offset_count = pipeline_layout->dynamic_offset_count;
7298 struct radv_shader *compute_shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
7306 *pPipeline = radv_pipeline_to_handle(&pipeline->base);