Lines Matching defs:shaders
138 struct radv_shader *shader = pipeline->base.shaders[pipeline->last_vgt_api_stage];
148 struct radv_shader *shader = pipeline->base.shaders[pipeline->last_vgt_api_stage];
219 if (pipeline->shaders[i])
220 radv_shader_destroy(device, pipeline->shaders[i]);
282 if (pipeline->shaders[i] && pipeline->shaders[i]->config.scratch_bytes_per_wave) {
286 MAX2(scratch_bytes_per_wave, pipeline->shaders[i]->config.scratch_bytes_per_wave);
290 radv_get_max_waves(device, pipeline->shaders[i], i));
1005 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
1104 if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.uses_sample_shading) {
1189 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
1408 pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
1421 if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
1423 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
1427 if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
2438 * Mesh shaders don't have any real vertex input, but they can produce
2728 struct radv_shader_info *gs_info = &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info;
2752 if (pipeline->shaders[MESA_SHADER_VERTEX])
2753 return pipeline->shaders[MESA_SHADER_VERTEX];
2754 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
2755 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
2756 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2757 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2759 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL])
2761 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
2762 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
2763 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2764 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2766 return pipeline->shaders[stage];
2774 return &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2778 return &pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2780 return &pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.outinfo;
2782 return &pipeline->base.shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2844 /* This pass is not suitable for mesh shaders, because it can't know
2858 * lower_io_to_temporaries for vertex shaders and inject the layer there. For geometry shaders,
3023 * output variables (some shaders have useless
3089 /* Remove PSIZ from shaders when it's not needed.
3207 /* ac_nir_lower_ngg ignores driver locations for mesh shaders,
3516 * mode. It can't be enabled for geometry shaders, for NGG
3517 * streamout or for vertex shaders that export the primitive ID
3842 * - In case of merged LSHS shaders, the LS and HS halves of the shader
4074 struct radv_shader *shader = pipeline->shaders[i];
4098 struct radv_shader *shader = pipeline->shaders[i];
4535 if (!(active_stages & (1 << s)) || pipeline->shaders[s])
4538 nir_shader *shaders[2] = { stages[s].nir, NULL };
4552 shaders[0] = stages[pre_stage].nir;
4553 shaders[1] = stages[s].nir;
4559 pipeline->shaders[s] = radv_shader_nir_to_asm(device, &stages[s], shaders, shader_count,
4565 active_stages &= ~(1 << shaders[0]->info.stage);
4566 if (shaders[1])
4567 active_stages &= ~(1 << shaders[1]->info.stage);
4625 /* Mesh shaders are mandatory in mesh shading pipelines. */
4627 /* Mesh shaders always need NGG. */
4694 /* Determine if shaders uses NGG before linking because it's needed for some NIR pass. */
4944 /* Compile NIR shaders to AMD assembly. */
4950 struct radv_shader *shader = pipeline->shaders[i];
4968 assert(!binaries[MESA_SHADER_COMPUTE] && !pipeline->shaders[MESA_SHADER_COMPUTE]);
4970 pipeline->shaders[MESA_SHADER_COMPUTE] = pipeline->gs_copy_shader;
4978 pipeline->gs_copy_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4979 pipeline->shaders[MESA_SHADER_COMPUTE] = NULL;
4988 if (radv_can_dump_shader_stats(device, stages[i].nir) && pipeline->shaders[i]) {
5624 const struct radv_shader *vs = pipeline->base.shaders[MESA_SHADER_TESS_EVAL]
5625 ? pipeline->base.shaders[MESA_SHADER_TESS_EVAL]
5626 : pipeline->base.shaders[MESA_SHADER_VERTEX];
5634 const struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
5743 unsigned num_lds_blocks = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks;
5768 struct radv_shader *es = pipeline->base.shaders[es_type];
5790 struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
5842 struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
5969 /* Skip shaders merged into HS/GS */
5970 vs = pipeline->base.shaders[MESA_SHADER_VERTEX];
5991 tcs = pipeline->base.shaders[MESA_SHADER_TESS_CTRL];
5992 tes = pipeline->base.shaders[MESA_SHADER_TESS_EVAL];
6026 pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; // TCS VERTICES OUT
6027 num_patches = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
6191 gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
6208 struct radv_shader *ms = pipeline->base.shaders[MESA_SHADER_MESH];
6289 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6393 assert(pipeline->base.shaders[MESA_SHADER_FRAGMENT]);
6395 ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6470 if (pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.needs_ms_scratch_ring)
6496 hs_size = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
6498 if (pipeline->base.shaders[MESA_SHADER_GEOMETRY]) {
6499 vs_size = gs_size = pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
6502 } else if (pipeline->base.shaders[MESA_SHADER_TESS_EVAL])
6503 vs_size = pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
6504 else if (pipeline->base.shaders[MESA_SHADER_VERTEX])
6505 vs_size = pipeline->base.shaders[MESA_SHADER_VERTEX]->info.wave_size;
6506 else if (pipeline->base.shaders[MESA_SHADER_MESH])
6507 vs_size = gs_size = pipeline->base.shaders[MESA_SHADER_MESH]->info.wave_size;
6562 primgroup_size = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
6565 &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
6573 if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
6625 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6666 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
6753 if (pipeline->base.shaders[MESA_SHADER_VERTEX])
6755 else if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL])
6760 const struct radv_shader *vs_shader = pipeline->base.shaders[MESA_SHADER_VERTEX];
6802 bool shader_exists = !!pipeline->base.shaders[i];
6840 si_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
6842 if (pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) {
6846 pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes._primitive_mode);
6850 si_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.output_prim);
6987 * GFX10 supports pixel shaders without exports by setting both the
6991 struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
7002 struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY];
7024 pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.has_ngg_culling;
7026 pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.force_vrs_per_vertex;
7215 struct radv_shader *shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
7298 struct radv_shader *compute_shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
7343 if (!pipeline->shaders[i])
7361 if (!pipeline->shaders[i])
7365 return pipeline->shaders[i];
7410 if (!pipeline->shaders[i])
7421 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
7435 if (pipeline->shaders[MESA_SHADER_TESS_CTRL] && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
7439 } else if (!pipeline->shaders[MESA_SHADER_TESS_CTRL] && !pipeline->shaders[MESA_SHADER_VERTEX]) {
7466 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;