Lines Matching defs:shader
138 struct radv_shader *shader = pipeline->base.shaders[pipeline->last_vgt_api_stage];
140 return shader->info.is_ngg;
148 struct radv_shader *shader = pipeline->base.shaders[pipeline->last_vgt_api_stage];
150 return shader->info.is_ngg_passthrough;
944 * reference value is written by the fragment shader. Tracking this
1092 * - If the interface of the fragment shader entry point of the
1198 * used by the fragment shader
1199 * 2) the fragment shader reads gl_SampleMaskIn because the
1922 /* Vertex input interface structs have to be ignored if the pipeline includes a mesh shader. */
2298 * other shader stages for LDS space. */
2436 /* Special case for mesh shader workgroups.
2440 * We need to precisely control the number of mesh shader workgroups
2447 * to the boundaries of the shader
2450 * - drawing 1 input vertex ~ launching 1 mesh shader workgroup
2452 * In the shader:
2454 * - input vertex id ~ workgroup id (in 1D - shader needs to calculate in 3D)
2511 * other shader stages for LDS space.
2513 * TODO: We should really take the shader's internal LDS use into
2845 * the mapping between API mesh shader invocations and output primitives.
2972 /* These variables are per-primitive when used with a mesh shader. */
3454 /* NGG passthrough mode should be disabled when culling and when the vertex shader exports the
3761 * enabled if either shader stage includes the execution mode.
3768 * shader stages."
3842 * - In case of merged LSHS shaders, the LS and HS halves of the shader
4074 struct radv_shader *shader = pipeline->shaders[i];
4075 if (!shader)
4078 code_size += align(shader->code_size, RADV_SHADER_ALLOC_ALIGNMENT);
4085 /* Allocate memory for all shader binaries. */
4092 /* Upload shader binaries. */
4098 struct radv_shader *shader = pipeline->shaders[i];
4099 if (!shader)
4102 shader->va = slab_va + slab_offset;
4105 if (!radv_shader_binary_upload(device, binaries[i], shader, dest_ptr))
4108 slab_offset += align(shader->code_size, RADV_SHADER_ALLOC_ALIGNMENT);
4141 /* VRS has no effect if there is no pixel shader. */
4662 .internal_nir = fs_b.shader,
4759 unreachable("Missing NGG shader stage.");
4950 struct radv_shader *shader = pipeline->shaders[i];
4951 if (!shader)
4957 shader->spirv = malloc(stages[i].spirv.size);
4958 memcpy(shader->spirv, stages[i].spirv.data, stages[i].spirv.size);
4959 shader->spirv_size = stages[i].spirv.size;
4963 /* Upload shader binaries. */
5069 unreachable("unknown shader");
5087 /* One shader engine */
5096 /* Two shader engines */
5105 /* Four shader engines */
5116 /* One shader engine */
5125 /* Two shader engines */
5134 /* Four shader engines */
5147 /* One shader engine */
5157 /* Two shader engines */
5168 /* Four shader engines */
5184 // One shader engine
5194 // Two shader engines
5205 // Four shader engines
5219 // One shader engine
5230 // Two shader engines
5242 // Four shader engines
5257 // One shader engine
5268 // Two shader engines
5280 // Four shader engines
5648 const struct radv_graphics_pipeline *pipeline, const struct radv_shader *shader)
5651 uint64_t va = radv_shader_get_va(shader);
5656 radeon_emit(cs, shader->config.rsrc1);
5657 radeon_emit(cs, shader->config.rsrc2);
5704 ac_compute_late_alloc(&pdevice->rad_info, false, false, shader->config.scratch_bytes_per_wave > 0,
5727 const struct radv_shader *shader)
5729 uint64_t va = radv_shader_get_va(shader);
5734 radeon_emit(cs, shader->config.rsrc1);
5735 radeon_emit(cs, shader->config.rsrc2);
5740 const struct radv_shader *shader)
5744 uint64_t va = radv_shader_get_va(shader);
5745 uint32_t rsrc2 = shader->config.rsrc2;
5754 radeon_emit(cs, shader->config.rsrc1);
5761 const struct radv_shader *shader)
5764 uint64_t va = radv_shader_get_va(shader);
5769 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
5774 radeon_emit(cs, shader->config.rsrc1);
5775 radeon_emit(cs, shader->config.rsrc2);
5895 ac_compute_late_alloc(&pdevice->rad_info, true, shader->info.has_ngg_culling,
5896 shader->config.scratch_bytes_per_wave > 0, &late_alloc_wave64, &cu_mask);
5923 if (shader->info.has_ngg_culling) {
5939 const struct radv_shader *shader)
5942 uint64_t va = radv_shader_get_va(shader);
5952 radeon_emit(cs, shader->config.rsrc1);
5953 radeon_emit(cs, shader->config.rsrc2);
5958 radeon_emit(cs, shader->config.rsrc1);
5959 radeon_emit(cs, shader->config.rsrc2);
6663 /* If the shader is using discard, turn off coarse shading because discard at 2x2 pixel
6779 struct radv_shader *shader = radv_get_shader(&pipeline->base, i);
6781 if (shader && shader->info.so.num_outputs > 0)
6782 return shader;
6804 /* We need this info for some stages even when the shader doesn't exist. */
6981 * 2) Performance: Every shader needs at least a NULL export, even when
7018 /* Find the last vertex shader stage that eventually uses streamout. */
7169 const struct radv_shader *shader)
7171 uint64_t va = radv_shader_get_va(shader);
7176 radeon_emit(cs, shader->config.rsrc1);
7177 radeon_emit(cs, shader->config.rsrc2);
7179 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3);
7185 struct radeon_cmdbuf *cs, const struct radv_shader *shader)
7194 shader->info.cs.block_size[0] * shader->info.cs.block_size[1] * shader->info.cs.block_size[2];
7195 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup, shader->info.wave_size);
7206 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[0]));
7207 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[1]));
7208 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[2]));
7215 struct radv_shader *shader = pipeline->base.shaders[MESA_SHADER_COMPUTE];
7221 radv_pipeline_emit_hw_cs(pdevice, cs, shader);
7222 radv_pipeline_emit_compute_state(pdevice, cs, shader);
7481 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
7501 struct radv_shader *shader =
7508 unsigned max_waves = radv_get_max_waves(device, shader, stage);
7526 s->value.u64 = shader->config.num_sgprs;
7534 s->value.u64 = shader->config.num_vgprs;
7542 s->value.u64 = shader->config.spilled_sgprs;
7550 s->value.u64 = shader->config.spilled_vgprs;
7558 s->value.u64 = shader->exec_size;
7566 s->value.u64 = shader->config.lds_size * lds_increment;
7574 s->value.u64 = shader->config.scratch_bytes_per_wave;
7586 if (shader->statistics) {
7593 s->value.u64 = shader->statistics[i];
7638 struct radv_shader *shader =
7649 desc_copy(p->description, "The optimized NIR shader(s)");
7650 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
7665 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
7671 if (p < end && shader->disasm_string) {
7675 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)