Lines Matching defs:outinfo
2570 if (!stages[MESA_SHADER_TESS_CTRL].nir && stages[MESA_SHADER_VERTEX].info.vs.outinfo.export_prim_id)
2774 return &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2776 return &pipeline->base.gs_copy_shader->info.vs.outinfo;
2778 return &pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2780 return &pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.outinfo;
2782 return &pipeline->base.shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
3449 if (es_stage == MESA_SHADER_VERTEX && stages[es_stage].info.vs.outinfo.export_prim_id)
3460 stages[es_stage].info.vs.outinfo.export_prim_id);
3564 struct radv_vs_output_info *outinfo = NULL;
3567 outinfo = &pre_ps_info->vs.outinfo;
3569 outinfo = &pre_ps_info->tes.outinfo;
3571 outinfo = &pre_ps_info->ms.outinfo;
3578 assert(outinfo);
3579 outinfo->export_clip_dists |= ps_clip_dists_in;
3582 outinfo->export_prim_id |= ps_prim_id_in;
4485 if (stages[MESA_SHADER_GEOMETRY].info.vs.outinfo.export_clip_dists)
4486 info.vs.outinfo.export_clip_dists = true;
5623 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
5637 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
5659 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
5661 clip_dist_mask = outinfo->clip_dist_mask;
5662 cull_dist_mask = outinfo->cull_dist_mask;
5665 bool misc_vec_ena = outinfo->writes_pointsize || outinfo->writes_layer ||
5666 outinfo->writes_viewport_index || outinfo->writes_primitive_shading_rate;
5670 nparams = MAX2(outinfo->param_exports, 1);
5674 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
5682 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
5684 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
5686 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
5690 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
5691 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
5692 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
5693 S_02881C_USE_VTX_VRS_RATE(outinfo->writes_primitive_shading_rate) |
5701 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, outinfo->writes_viewport_index);
5777 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
5779 clip_dist_mask = outinfo->clip_dist_mask;
5780 cull_dist_mask = outinfo->cull_dist_mask;
5783 bool misc_vec_ena = outinfo->writes_pointsize || outinfo->writes_layer ||
5784 outinfo->writes_viewport_index || outinfo->writes_primitive_shading_rate;
5785 bool es_enable_prim_id = outinfo->export_prim_id || (es && es->info.uses_prim_id);
5796 bool no_pc_export = outinfo->param_exports == 0 && outinfo->prim_param_exports == 0;
5797 unsigned num_params = MAX2(outinfo->param_exports, 1);
5798 unsigned num_prim_params = outinfo->prim_param_exports;
5806 if (outinfo->writes_layer_per_primitive ||
5807 outinfo->writes_viewport_index_per_primitive ||
5808 outinfo->writes_primitive_shading_rate_per_primitive)
5816 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
5818 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
5820 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
5824 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
5825 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
5826 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
5827 S_02881C_USE_VTX_VRS_RATE(outinfo->writes_primitive_shading_rate) |
5836 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
5926 if (outinfo->param_exports > 4)
5928 else if (outinfo->param_exports > 2)
6245 single_slot_to_ps_input(const struct radv_vs_output_info *outinfo,
6249 unsigned vs_offset = outinfo->vs_output_param_offset[slot];
6265 input_mask_to_ps_inputs(const struct radv_vs_output_info *outinfo, const struct radv_shader *ps,
6269 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
6290 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
6297 single_slot_to_ps_input(outinfo, VARYING_SLOT_PRIMITIVE_ID, ps_input_cntl, &ps_offset,
6301 single_slot_to_ps_input(outinfo, VARYING_SLOT_LAYER, ps_input_cntl, &ps_offset,
6305 single_slot_to_ps_input(outinfo, VARYING_SLOT_VIEWPORT, ps_input_cntl, &ps_offset,
6312 single_slot_to_ps_input(outinfo, VARYING_SLOT_CLIP_DIST0, ps_input_cntl, &ps_offset,
6316 single_slot_to_ps_input(outinfo, VARYING_SLOT_CLIP_DIST1, ps_input_cntl, &ps_offset,
6320 input_mask_to_ps_inputs(outinfo, ps, ps->info.ps.input_mask,
6326 single_slot_to_ps_input(outinfo, VARYING_SLOT_PRIMITIVE_ID, ps_input_cntl, &ps_offset,
6330 single_slot_to_ps_input(outinfo, VARYING_SLOT_LAYER, ps_input_cntl, &ps_offset,
6334 single_slot_to_ps_input(outinfo, VARYING_SLOT_VIEWPORT, ps_input_cntl, &ps_offset,
6337 input_mask_to_ps_inputs(outinfo, ps, ps->info.ps.input_per_primitive_mask,
6604 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
6612 outinfo &&
6613 (outinfo->writes_viewport_index_per_primitive ||
6614 outinfo->writes_layer_per_primitive ||
6615 outinfo->writes_primitive_shading_rate_per_primitive);