Lines Matching defs:info
102 const struct radv_graphics_pipeline_info *info)
104 return info->fsr.size.width != 1 || info->fsr.size.height != 1 ||
105 info->fsr.combiner_ops[0] != VK_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP_KHR ||
106 info->fsr.combiner_ops[1] != VK_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP_KHR;
111 const struct radv_graphics_pipeline_info *info)
113 return radv_is_static_vrs_enabled(pipeline, info) ||
140 return shader->info.is_ngg;
150 return shader->info.is_ngg_passthrough;
535 const struct radv_graphics_pipeline_info *info)
540 for (unsigned i = 0; i < info->ri.color_att_count; ++i) {
542 VkFormat fmt = info->ri.color_att_formats[i];
695 const struct radv_graphics_pipeline_info *info)
703 if (info->cb.logic_op_enable)
704 cb_color_control |= S_028808_ROP3(info->cb.logic_op);
721 if (info->ms.alpha_to_coverage_enable) {
727 for (i = 0; i < info->cb.att_count; i++) {
730 unsigned eqRGB = info->cb.att[i].color_blend_op;
731 unsigned srcRGB = info->cb.att[i].src_color_blend_factor;
732 unsigned dstRGB = info->cb.att[i].dst_color_blend_factor;
733 unsigned eqA = info->cb.att[i].alpha_blend_op;
734 unsigned srcA = info->cb.att[i].src_alpha_blend_factor;
735 unsigned dstA = info->cb.att[i].dst_alpha_blend_factor;
740 if (!info->cb.att[i].color_write_mask)
749 blend.cb_target_mask |= (unsigned)info->cb.att[i].color_write_mask << (4 * i);
751 if (!info->cb.att[i].blend_enable) {
834 for (i = info->cb.att_count; i < 8; i++) {
852 if (blend.mrt0_is_dual_src || info->cb.logic_op_enable ||
862 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend, info);
886 radv_pipeline_color_samples( const struct radv_graphics_pipeline_info *info)
888 if (info->color_att_samples && radv_pipeline_has_color_attachments(&info->ri)) {
889 return info->color_att_samples;
892 return info->ms.raster_samples;
896 radv_pipeline_depth_samples(const struct radv_graphics_pipeline_info *info)
898 if (info->ds_att_samples && radv_pipeline_has_ds_attachments(&info->ri)) {
899 return info->ds_att_samples;
902 return info->ms.raster_samples;
906 radv_pipeline_get_ps_iter_samples(const struct radv_graphics_pipeline_info *info)
909 uint32_t num_samples = radv_pipeline_color_samples(info);
911 if (info->ms.sample_shading_enable) {
912 ps_iter_samples = ceilf(info->ms.min_sample_shading * num_samples);
926 radv_writes_stencil(const struct radv_stencil_op_info *info)
928 return info->write_mask &&
929 (info->fail_op != VK_STENCIL_OP_KEEP || info->pass_op != VK_STENCIL_OP_KEEP ||
930 info->depth_fail_op != VK_STENCIL_OP_KEEP);
952 radv_order_invariant_stencil_state(const struct radv_stencil_op_info *info)
959 return !info->write_mask ||
961 (info->compare_op == VK_COMPARE_OP_ALWAYS &&
962 radv_order_invariant_stencil_op(info->pass_op) &&
963 radv_order_invariant_stencil_op(info->depth_fail_op)) ||
964 (info->compare_op == VK_COMPARE_OP_NEVER &&
965 radv_order_invariant_stencil_op(info->fail_op));
982 const struct radv_graphics_pipeline_info *info)
990 if (colormask && info->cb.logic_op_enable)
1003 bool has_stencil = info->ri.stencil_att_format != VK_FORMAT_UNDEFINED;
1010 bool zfunc_is_ordered = info->ds.depth_compare_op == VK_COMPARE_OP_NEVER ||
1011 info->ds.depth_compare_op == VK_COMPARE_OP_LESS ||
1012 info->ds.depth_compare_op == VK_COMPARE_OP_LESS_OR_EQUAL ||
1013 info->ds.depth_compare_op == VK_COMPARE_OP_GREATER ||
1014 info->ds.depth_compare_op == VK_COMPARE_OP_GREATER_OR_EQUAL;
1015 bool depth_write_enabled = radv_is_depth_write_enabled(&info->ds);
1016 bool stencil_write_enabled = radv_is_stencil_write_enabled(&info->ds);
1021 (!depth_write_enabled && radv_order_invariant_stencil_state(&info->ds.front) &&
1022 radv_order_invariant_stencil_state(&info->ds.back));
1031 (info->ds.depth_compare_op == VK_COMPARE_OP_ALWAYS ||
1032 info->ds.depth_compare_op == VK_COMPARE_OP_NEVER));
1035 (info->ds.depth_compare_op == VK_COMPARE_OP_ALWAYS ||
1036 info->ds.depth_compare_op == VK_COMPARE_OP_NEVER);
1045 if (ps && ps->info.ps.writes_memory && ps->info.ps.early_fragment_test &&
1076 const struct radv_graphics_pipeline_info *info,
1082 const VkConservativeRasterizationModeEXT mode = info->rs.conservative_mode;
1086 ms->num_samples = info->ms.raster_samples;
1104 if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.uses_sample_shading) {
1107 ps_iter_samples = radv_pipeline_get_ps_iter_samples(info);
1110 if (info->rs.order == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1119 out_of_order_rast = radv_pipeline_out_of_order_rast(pipeline, blend, info);
1145 S_028A48_LINE_STIPPLE_ENABLE(info->rs.stippled_line_enable);
1147 if (info->rs.line_raster_mode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT &&
1162 uint32_t z_samples = radv_pipeline_depth_samples(info);
1181 ms->pa_sc_aa_mask[0] = info->ms.sample_mask | ((uint32_t)info->ms.sample_mask << 16);
1182 ms->pa_sc_aa_mask[1] = info->ms.sample_mask | ((uint32_t)info->ms.sample_mask << 16);
1187 const struct radv_graphics_pipeline_info *info)
1193 if (info->ms.sample_shading_enable ||
1194 ps->info.ps.uses_sample_shading || ps->info.ps.reads_sample_mask_in) {
1339 const struct radv_graphics_pipeline_info *info)
1341 bool has_color_att = radv_pipeline_has_color_attachments(&info->ri);
1342 bool raster_enabled = !info->rs.discard_enable ||
1366 if (!info->rs.depth_bias_enable &&
1370 if (!info->ds.depth_bounds_test_enable &&
1374 if (!info->ds.stencil_test_enable &&
1379 if (!info->dr.count)
1382 if (!info->ms.sample_locs_enable)
1385 if (!info->rs.stippled_line_enable)
1388 if (!radv_is_vrs_enabled(pipeline, info))
1391 if (!has_color_att || !radv_pipeline_is_blend_enabled(pipeline, &info->cb))
1408 pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
1421 if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
1423 if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
1427 if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
1428 radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
1500 struct radv_vertex_input_info info = {0};
1518 info.binding_stride[desc->binding] = desc->stride;
1537 info.instance_rate_inputs |= 1u << location;
1538 info.instance_rate_divisors[location] = instance_rate_divisors[binding];
1543 &post_shuffle, &info.vertex_alpha_adjust[location]);
1545 info.vertex_attribute_formats[location] = data_format | (num_format << 4);
1546 info.vertex_attribute_bindings[location] = desc->binding;
1547 info.vertex_attribute_offsets[location] = desc->offset;
1557 info.vertex_binding_align[desc->binding] =
1558 MAX2(info.vertex_binding_align[desc->binding], attrib_align);
1576 info.vertex_attribute_strides[location] = radv_get_attrib_stride(vi, desc->binding);
1580 info.vertex_post_shuffle |= 1 << location;
1583 info.attrib_ends[desc->location] = end;
1584 if (info.binding_stride[desc->binding])
1585 info.attrib_index_offset[desc->location] =
1586 desc->offset / info.binding_stride[desc->binding];
1587 info.attrib_bindings[desc->location] = desc->binding;
1591 return info;
1599 struct radv_input_assembly_info info = {0};
1601 info.primitive_topology = si_translate_prim(ia->topology);
1602 info.primitive_restart_enable = !!ia->primitiveRestartEnable;
1604 return info;
1614 struct radv_tessellation_info info = {0};
1617 info.patch_control_points = ts->patchControlPoints;
1622 info.domain_origin = domain_origin_state->domainOrigin;
1626 return info;
1634 struct radv_viewport_info info = {0};
1638 typed_memcpy(info.viewports, vp->pViewports, vp->viewportCount);
1640 info.viewport_count = vp->viewportCount;
1643 typed_memcpy(info.scissors, vp->pScissors, vp->scissorCount);
1645 info.scissor_count = vp->scissorCount;
1650 info.negative_one_to_one = !!depth_clip_control->negativeOneToOne;
1654 return info;
1662 struct radv_rasterization_info info = {0};
1664 info.discard_enable = rs->rasterizerDiscardEnable;
1665 info.front_face = rs->frontFace;
1666 info.cull_mode = rs->cullMode;
1667 info.polygon_mode = si_translate_fill(rs->polygonMode);
1668 info.depth_bias_enable = rs->depthBiasEnable;
1669 info.depth_clamp_enable = rs->depthClampEnable;
1670 info.line_width = rs->lineWidth;
1671 info.depth_bias_constant_factor = rs->depthBiasConstantFactor;
1672 info.depth_bias_clamp = rs->depthBiasClamp;
1673 info.depth_bias_slope_factor = rs->depthBiasSlopeFactor;
1674 info.depth_clip_disable = rs->depthClampEnable;
1680 info.provoking_vtx_last = true;
1686 info.conservative_mode = conservative_raster->conservativeRasterizationMode;
1692 info.stippled_line_enable = rast_line_info->stippledLineEnable;
1693 info.line_raster_mode = rast_line_info->lineRasterizationMode;
1694 info.line_stipple_factor = rast_line_info->lineStippleFactor;
1695 info.line_stipple_pattern = rast_line_info->lineStipplePattern;
1701 info.depth_clip_disable = !depth_clip_state->depthClipEnable;
1707 info.order = raster_order->rasterizationOrder;
1710 return info;
1719 struct radv_discard_rectangle_info info = {0};
1722 info.mode = discard_rectangle_info->discardRectangleMode;
1724 typed_memcpy(info.rects, discard_rectangle_info->pDiscardRectangles,
1727 info.count = discard_rectangle_info->discardRectangleCount;
1730 return info;
1738 struct radv_multisample_info info = {0};
1741 info.raster_samples = ms->rasterizationSamples;
1742 info.sample_shading_enable = ms->sampleShadingEnable;
1743 info.min_sample_shading = ms->minSampleShading;
1744 info.alpha_to_coverage_enable = ms->alphaToCoverageEnable;
1746 info.sample_mask = ms->pSampleMask[0] & 0xffff;
1748 info.sample_mask = 0xffff;
1757 info.sample_locs_enable = sample_location_info->sampleLocationsEnable;
1763 info.sample_locs_per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1764 info.sample_locs_grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1766 info.sample_locs[i] = pSampleLocationsInfo->pSampleLocations[i];
1768 info.sample_locs_count = pSampleLocationsInfo->sampleLocationsCount;
1772 info.raster_samples = VK_SAMPLE_COUNT_1_BIT;
1775 return info;
1785 struct radv_depth_stencil_info info = {0};
1790 info.depth_bounds_test_enable = ds->depthBoundsTestEnable;
1791 info.depth_bounds.min = ds->minDepthBounds;
1792 info.depth_bounds.max = ds->maxDepthBounds;
1793 info.stencil_test_enable = ds->stencilTestEnable;
1794 info.front.fail_op = ds->front.failOp;
1795 info.front.pass_op = ds->front.passOp;
1796 info.front.depth_fail_op = ds->front.depthFailOp;
1797 info.front.compare_op = ds->front.compareOp;
1798 info.front.compare_mask = ds->front.compareMask;
1799 info.front.write_mask = ds->front.writeMask;
1800 info.front.reference = ds->front.reference;
1801 info.back.fail_op = ds->back.failOp;
1802 info.back.pass_op = ds->back.passOp;
1803 info.back.depth_fail_op = ds->back.depthFailOp;
1804 info.back.compare_op = ds->back.compareOp;
1805 info.back.compare_mask = ds->back.compareMask;
1806 info.back.write_mask = ds->back.writeMask;
1807 info.back.reference = ds->back.reference;
1808 info.depth_test_enable = ds->depthTestEnable;
1809 info.depth_write_enable = ds->depthWriteEnable;
1810 info.depth_compare_op = ds->depthCompareOp;
1813 return info;
1822 struct radv_rendering_info info = {0};
1824 info.view_mask = ri->viewMask;
1826 info.color_att_formats[i] = ri->pColorAttachmentFormats[i];
1828 info.color_att_count = ri->colorAttachmentCount;
1829 info.depth_att_format = ri->depthAttachmentFormat;
1830 info.stencil_att_format = ri->stencilAttachmentFormat;
1832 return info;
1843 struct radv_color_blend_info info = {0};
1857 info.att[i].color_write_mask = att->colorWriteMask;
1858 info.att[i].blend_enable = att->blendEnable;
1859 info.att[i].color_blend_op = si_translate_blend_function(att->colorBlendOp);
1860 info.att[i].alpha_blend_op = si_translate_blend_function(att->alphaBlendOp);
1861 info.att[i].src_color_blend_factor =
1863 info.att[i].dst_color_blend_factor =
1865 info.att[i].src_alpha_blend_factor =
1867 info.att[i].dst_alpha_blend_factor =
1870 info.att_count = cb->attachmentCount;
1873 info.blend_constants[i] = cb->blendConstants[i];
1876 info.logic_op_enable = cb->logicOpEnable;
1877 if (info.logic_op_enable)
1878 info.logic_op = si_translate_blend_logic_op(cb->logicOp);
1884 info.color_write_enable |=
1888 info.color_write_enable = 0xffffffffu;
1892 return info;
1901 struct radv_fragment_shading_rate_info info = {0};
1904 info.size = shading_rate->fragmentSize;
1906 info.combiner_ops[i] = shading_rate->combinerOps[i];
1908 info.size = (VkExtent2D){ 1, 1 };
1909 info.combiner_ops[0] = VK_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP_KHR;
1910 info.combiner_ops[1] = VK_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP_KHR;
1913 return info;
1920 struct radv_graphics_pipeline_info info = {0};
1924 info.vi = radv_pipeline_init_vertex_input_info(pipeline, pCreateInfo);
1925 info.ia = radv_pipeline_init_input_assembly_info(pipeline, pCreateInfo);
1928 info.ts = radv_pipeline_init_tessellation_info(pipeline, pCreateInfo);
1929 info.vp = radv_pipeline_init_viewport_info(pipeline, pCreateInfo);
1930 info.rs = radv_pipeline_init_rasterization_info(pipeline, pCreateInfo);
1931 info.dr = radv_pipeline_init_discard_rectangle_info(pipeline, pCreateInfo);
1933 info.ms = radv_pipeline_init_multisample_info(pipeline, pCreateInfo);
1934 info.ds = radv_pipeline_init_depth_stencil_info(pipeline, pCreateInfo);
1935 info.ri = radv_pipeline_init_rendering_info(pipeline, pCreateInfo);
1936 info.cb = radv_pipeline_init_color_blend_info(pipeline, pCreateInfo);
1938 info.fsr = radv_pipeline_init_fragment_shading_rate_info(pipeline, pCreateInfo);
1945 if (info.ri.color_att_formats[i] != VK_FORMAT_UNDEFINED) {
1946 info.color_att_samples = MAX2(info.color_att_samples, sample_info->pColorAttachmentSamples[i]);
1949 info.ds_att_samples = sample_info->depthStencilAttachmentSamples;
1952 return info;
1957 const struct radv_graphics_pipeline_info *info)
1964 const struct radv_graphics_pipeline_info *info)
1966 uint64_t needed_states = radv_pipeline_needed_dynamic_state(pipeline, info);
1977 dynamic->viewport.count = info->vp.viewport_count;
1979 typed_memcpy(dynamic->viewport.viewports, info->vp.viewports, info->vp.viewport_count);
1987 dynamic->scissor.count = info->vp.scissor_count;
1989 typed_memcpy(dynamic->scissor.scissors, info->vp.scissors, info->vp.scissor_count);
1994 dynamic->line_width = info->rs.line_width;
1998 dynamic->depth_bias.bias = info->rs.depth_bias_constant_factor;
1999 dynamic->depth_bias.clamp = info->rs.depth_bias_clamp;
2000 dynamic->depth_bias.slope = info->rs.depth_bias_slope_factor;
2010 typed_memcpy(dynamic->blend_constants, info->cb.blend_constants, 4);
2014 dynamic->cull_mode = info->rs.cull_mode;
2018 dynamic->front_face = info->rs.front_face;
2022 dynamic->primitive_topology = info->ia.primitive_topology;
2037 if (needed_states && radv_pipeline_has_ds_attachments(&info->ri)) {
2039 dynamic->depth_bounds.min = info->ds.depth_bounds.min;
2040 dynamic->depth_bounds.max = info->ds.depth_bounds.max;
2044 dynamic->stencil_compare_mask.front = info->ds.front.compare_mask;
2045 dynamic->stencil_compare_mask.back = info->ds.back.compare_mask;
2049 dynamic->stencil_write_mask.front = info->ds.front.write_mask;
2050 dynamic->stencil_write_mask.back = info->ds.back.write_mask;
2054 dynamic->stencil_reference.front = info->ds.front.reference;
2055 dynamic->stencil_reference.back = info->ds.back.reference;
2059 dynamic->depth_test_enable = info->ds.depth_test_enable;
2063 dynamic->depth_write_enable = info->ds.depth_write_enable;
2067 dynamic->depth_compare_op = info->ds.depth_compare_op;
2071 dynamic->depth_bounds_test_enable = info->ds.depth_bounds_test_enable;
2075 dynamic->stencil_test_enable = info->ds.stencil_test_enable;
2079 dynamic->stencil_op.front.compare_op = info->ds.front.compare_op;
2080 dynamic->stencil_op.front.fail_op = info->ds.front.fail_op;
2081 dynamic->stencil_op.front.pass_op = info->ds.front.pass_op;
2082 dynamic->stencil_op.front.depth_fail_op = info->ds.front.depth_fail_op;
2084 dynamic->stencil_op.back.compare_op = info->ds.back.compare_op;
2085 dynamic->stencil_op.back.fail_op = info->ds.back.fail_op;
2086 dynamic->stencil_op.back.pass_op = info->ds.back.pass_op;
2087 dynamic->stencil_op.back.depth_fail_op = info->ds.back.depth_fail_op;
2092 dynamic->discard_rectangle.count = info->dr.count;
2094 typed_memcpy(dynamic->discard_rectangle.rectangles, info->dr.rects, info->dr.count);
2099 if (info->ms.sample_locs_enable) {
2100 dynamic->sample_location.per_pixel = info->ms.sample_locs_per_pixel;
2101 dynamic->sample_location.grid_size = info->ms.sample_locs_grid_size;
2102 dynamic->sample_location.count = info->ms.sample_locs_count;
2103 typed_memcpy(&dynamic->sample_location.locations[0], info->ms.sample_locs,
2104 info->ms.sample_locs_count);
2109 dynamic->line_stipple.factor = info->rs.line_stipple_factor;
2110 dynamic->line_stipple.pattern = info->rs.line_stipple_pattern;
2118 dynamic->fragment_shading_rate.size = info->fsr.size;
2120 dynamic->fragment_shading_rate.combiner_ops[i] = info->fsr.combiner_ops[i];
2124 dynamic->depth_bias_enable = info->rs.depth_bias_enable;
2128 dynamic->primitive_restart_enable = info->ia.primitive_restart_enable;
2132 dynamic->rasterizer_discard_enable = info->rs.discard_enable;
2135 if (radv_pipeline_has_color_attachments(&info->ri) && states & RADV_DYNAMIC_LOGIC_OP) {
2136 if (info->cb.logic_op_enable) {
2137 dynamic->logic_op = info->cb.logic_op;
2144 dynamic->color_write_enable = info->cb.color_write_enable;
2152 const struct radv_graphics_pipeline_info *info)
2157 S_028814_FACE(info->rs.front_face) |
2158 S_028814_CULL_FRONT(!!(info->rs.cull_mode & VK_CULL_MODE_FRONT_BIT)) |
2159 S_028814_CULL_BACK(!!(info->rs.cull_mode & VK_CULL_MODE_BACK_BIT)) |
2160 S_028814_POLY_MODE(info->rs.polygon_mode != V_028814_X_DRAW_TRIANGLES) |
2161 S_028814_POLYMODE_FRONT_PTYPE(info->rs.polygon_mode) |
2162 S_028814_POLYMODE_BACK_PTYPE(info->rs.polygon_mode) |
2163 S_028814_POLY_OFFSET_FRONT_ENABLE(info->rs.depth_bias_enable) |
2164 S_028814_POLY_OFFSET_BACK_ENABLE(info->rs.depth_bias_enable) |
2165 S_028814_POLY_OFFSET_PARA_ENABLE(info->rs.depth_bias_enable) |
2166 S_028814_PROVOKING_VTX_LAST(info->rs.provoking_vtx_last);
2171 S_028814_KEEP_TOGETHER_ENABLE(info->rs.polygon_mode != V_028814_X_DRAW_TRIANGLES);
2176 S_028810_ZCLIP_NEAR_DISABLE(info->rs.depth_clip_disable) |
2177 S_028810_ZCLIP_FAR_DISABLE(info->rs.depth_clip_disable) |
2178 S_028810_DX_RASTERIZATION_KILL(info->rs.discard_enable) |
2182 info->rs.conservative_mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT;
2185 if (!info->rs.depth_clamp_enable) {
2190 if (info->rs.depth_clip_disable ||
2201 const struct radv_graphics_pipeline_info *info)
2207 bool has_depth_attachment = info->ri.depth_att_format != VK_FORMAT_UNDEFINED;
2208 bool has_stencil_attachment = info->ri.stencil_att_format != VK_FORMAT_UNDEFINED;
2212 ds_state.db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(info->ms.raster_samples > 2);
2217 db_depth_control = S_028800_Z_ENABLE(info->ds.depth_test_enable) |
2218 S_028800_Z_WRITE_ENABLE(info->ds.depth_write_enable) |
2219 S_028800_ZFUNC(info->ds.depth_compare_op) |
2220 S_028800_DEPTH_BOUNDS_ENABLE(info->ds.depth_bounds_test_enable);
2223 if (has_stencil_attachment && info->ds.stencil_test_enable) {
2225 db_depth_control |= S_028800_STENCILFUNC(info->ds.front.compare_op);
2226 db_depth_control |= S_028800_STENCILFUNC_BF(info->ds.back.compare_op);
2237 unsigned num_samples = MAX2(radv_pipeline_color_samples(info),
2238 radv_pipeline_depth_samples(info));
2272 struct radv_shader_info *gs_info = &stages[MESA_SHADER_GEOMETRY].info;
2279 es_info = has_tess ? &stages[MESA_SHADER_TESS_EVAL].info.tes.es_info
2280 : &stages[MESA_SHADER_VERTEX].info.vs.es_info;
2386 pdevice->rad_info.gfx_level, stages[es_stage].info.wave_size,
2388 stages[es_stage].info.workgroup_size = workgroup_size;
2389 stages[MESA_SHADER_GEOMETRY].info.workgroup_size = workgroup_size;
2408 return gs->info.gs.vertices_in;
2414 if (tes->info.tess.point_mode)
2416 if (tes->info.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES)
2468 ngg->max_out_verts = ms->info.mesh.max_vertices_out;
2471 ngg->prim_amp_factor = ms->info.mesh.max_primitives_out;
2479 ac_compute_cs_workgroup_size(ms->info.workgroup_size, false, UINT32_MAX);
2481 stage->info.workgroup_size = MAX2(min_ngg_workgroup_size, api_workgroup_size);
2489 struct radv_shader_info *gs_info = &stages[MESA_SHADER_GEOMETRY].info;
2560 ? &stages[MESA_SHADER_TESS_EVAL].info.so
2561 : &stages[MESA_SHADER_VERTEX].info.so;
2570 if (!stages[MESA_SHADER_TESS_CTRL].nir && stages[MESA_SHADER_VERTEX].info.vs.outinfo.export_prim_id)
2614 wavesize = stages[MESA_SHADER_TESS_CTRL].nir ? stages[MESA_SHADER_TESS_EVAL].info.wave_size
2615 : stages[MESA_SHADER_VERTEX].info.wave_size;
2710 stages[MESA_SHADER_GEOMETRY].info.workgroup_size = workgroup_size;
2711 stages[es_stage].info.workgroup_size = workgroup_size;
2728 struct radv_shader_info *gs_info = &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info;
2774 return &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2776 return &pipeline->base.gs_copy_shader->info.vs.outinfo;
2778 return &pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2780 return &pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.outinfo;
2782 return &pipeline->base.shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2848 if (nir->info.stage == MESA_SHADER_MESH)
2867 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
2891 nir->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_LAYER);
2894 if (nir->info.stage == MESA_SHADER_VERTEX)
2897 if (nir->info.stage == MESA_SHADER_VERTEX && progress)
2925 nir->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_ID);
2984 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2985 unsigned last = ordered_shaders[0]->info.stage;
2987 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2988 ordered_shaders[1]->info.has_transform_feedback_varyings)
3000 if (ordered_shaders[i]->info.stage != first)
3003 if (ordered_shaders[i]->info.stage != last)
3013 if (ordered_shaders[i]->info.stage != last) {
3030 if (ordered_shaders[i]->info.stage == MESA_SHADER_TESS_CTRL)
3044 (stages[MESA_SHADER_FRAGMENT].nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID) &&
3045 !(stages[last_vgt_api_stage].nir->info.outputs_written & VARYING_BIT_PRIMITIVE_ID) &&
3046 ((last_vgt_api_stage == MESA_SHADER_VERTEX && !stages[MESA_SHADER_VERTEX].info.is_ngg) ||
3047 (last_vgt_api_stage == MESA_SHADER_TESS_EVAL && !stages[MESA_SHADER_TESS_EVAL].info.is_ngg))) {
3056 shader_info *info = &ordered_shaders[i]->info;
3059 if (info->stage == MESA_SHADER_FRAGMENT) {
3074 info->outputs_written &= ~BITFIELD64_BIT(var->data.location);
3092 if (uses_xfb || !(info->outputs_written & VARYING_BIT_PSIZ))
3097 ordered_shaders[i - 1]->info.inputs_read & VARYING_BIT_PSIZ;
3099 info->stage == last_vgt_api_stage &&
3100 ((info->stage == MESA_SHADER_VERTEX && pipeline_key->vs.topology == V_008958_DI_PT_POINTLIST) ||
3101 (info->stage == MESA_SHADER_TESS_EVAL && info->tess.point_mode) ||
3102 (info->stage == MESA_SHADER_GEOMETRY && info->gs.output_primitive == SHADER_PRIM_POINTS) ||
3103 (info->stage == MESA_SHADER_MESH && info->mesh.primitive_type == SHADER_PRIM_POINTS));
3113 info->outputs_written &= ~VARYING_BIT_PSIZ;
3123 (stages[MESA_SHADER_FRAGMENT].nir->info.inputs_read & VARYING_BIT_VIEWPORT) &&
3124 !(stages[last_vgt_api_stage].nir->info.outputs_written & VARYING_BIT_VIEWPORT)) {
3130 !(stages[last_vgt_api_stage].nir->info.outputs_written &
3154 if (ordered_shaders[i]->info.stage == MESA_SHADER_MESH) {
3159 if (ordered_shaders[i]->info.stage == MESA_SHADER_TESS_CTRL ||
3160 ordered_shaders[i]->info.stage == MESA_SHADER_MESH ||
3161 (ordered_shaders[i]->info.stage == MESA_SHADER_VERTEX && has_geom_tess) ||
3162 (ordered_shaders[i]->info.stage == MESA_SHADER_TESS_EVAL && merged_gs)) {
3164 if (ordered_shaders[i]->info.stage == MESA_SHADER_TESS_CTRL)
3168 if (ordered_shaders[i - 1]->info.stage == MESA_SHADER_GEOMETRY ||
3169 ordered_shaders[i - 1]->info.stage == MESA_SHADER_TESS_CTRL ||
3170 ordered_shaders[i - 1]->info.stage == MESA_SHADER_TESS_EVAL) {
3242 stages[MESA_SHADER_VERTEX].info.vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
3243 stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
3244 stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
3245 stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
3246 stages[MESA_SHADER_TESS_EVAL].info.tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
3247 stages[MESA_SHADER_TESS_EVAL].info.tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
3250 stages[vs_info_idx].info.vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
3251 stages[tes_info_idx].info.tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
3252 stages[tes_info_idx].info.tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
3258 stages[MESA_SHADER_TESS_EVAL].info.tes.num_linked_outputs = tes2gs.num_linked_io_vars;
3259 stages[MESA_SHADER_GEOMETRY].info.gs.num_linked_inputs = tes2gs.num_linked_io_vars;
3262 stages[tes_info_idx].info.tes.num_linked_outputs = tes2gs.num_linked_io_vars;
3268 stages[MESA_SHADER_VERTEX].info.vs.num_linked_outputs = vs2gs.num_linked_io_vars;
3269 stages[MESA_SHADER_GEOMETRY].info.gs.num_linked_inputs = vs2gs.num_linked_io_vars;
3272 stages[vs_info_idx].info.vs.num_linked_outputs = vs2gs.num_linked_io_vars;
3305 const struct radv_graphics_pipeline_info *info,
3311 key.has_multiview_view_index = !!info->ri.view_mask;
3318 key.vs.instance_rate_inputs = info->vi.instance_rate_inputs;
3319 key.vs.vertex_post_shuffle = info->vi.vertex_post_shuffle;
3322 key.vs.instance_rate_divisors[i] = info->vi.instance_rate_divisors[i];
3323 key.vs.vertex_attribute_formats[i] = info->vi.vertex_attribute_formats[i];
3324 key.vs.vertex_attribute_bindings[i] = info->vi.vertex_attribute_bindings[i];
3325 key.vs.vertex_attribute_offsets[i] = info->vi.vertex_attribute_offsets[i];
3326 key.vs.vertex_attribute_strides[i] = info->vi.vertex_attribute_strides[i];
3327 key.vs.vertex_alpha_adjust[i] = info->vi.vertex_alpha_adjust[i];
3331 key.vs.vertex_binding_align[i] = info->vi.vertex_binding_align[i];
3334 key.tcs.tess_input_vertices = info->ts.patch_control_points;
3336 if (info->ms.raster_samples > 1) {
3337 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(info);
3338 key.ps.num_samples = info->ms.raster_samples;
3350 key.ps.alpha_to_coverage_via_mrtz = info->ms.alpha_to_coverage_enable;
3353 key.vs.topology = info->ia.primitive_topology;
3356 key.vs.provoking_vtx_last = info->rs.provoking_vtx_last;
3373 if ((radv_is_vrs_enabled(pipeline, info) || device->force_vrs_enabled) &&
3392 const struct radv_shader_info *info)
3394 if (stage == MESA_SHADER_GEOMETRY && !info->is_ngg)
3397 return info->cs.subgroup_size;
3408 const struct radv_shader_info *info)
3410 if (stage == MESA_SHADER_COMPUTE && info->cs.subgroup_size)
3411 return info->cs.subgroup_size;
3427 stages[MESA_SHADER_FRAGMENT].nir ? stages[MESA_SHADER_FRAGMENT].nir->info.inputs_read : 0;
3432 num_vertices_per_prim = stages[es_stage].nir->info.tess.point_mode ? 1
3433 : stages[es_stage].nir->info.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES ? 2
3436 stages[es_stage].info.has_ngg_culling = radv_consider_culling(
3437 pdevice, stages[es_stage].nir, ps_inputs_read, num_vertices_per_prim, &stages[es_stage].info) &&
3441 stages[es_stage].info.has_ngg_early_prim_export = exec_list_is_singular(&impl->body);
3444 const struct gfx10_ngg_info *ngg_info = &stages[es_stage].info.ngg_info;
3449 if (es_stage == MESA_SHADER_VERTEX && stages[es_stage].info.vs.outinfo.export_prim_id)
3451 stages[es_stage].info.num_lds_blocks_when_not_culling =
3457 stages[es_stage].info.is_ngg_passthrough = stages[es_stage].info.is_ngg_passthrough &&
3458 !stages[es_stage].info.has_ngg_culling &&
3460 stages[es_stage].info.vs.outinfo.export_prim_id);
3473 stages[MESA_SHADER_TESS_EVAL].info.is_ngg = true;
3475 stages[MESA_SHADER_VERTEX].info.is_ngg = true;
3477 stages[MESA_SHADER_MESH].info.is_ngg = true;
3481 stages[MESA_SHADER_GEOMETRY].nir->info.gs.invocations *
3482 stages[MESA_SHADER_GEOMETRY].nir->info.gs.vertices_out >
3489 stages[MESA_SHADER_TESS_EVAL].info.is_ngg = false;
3510 stages[MESA_SHADER_TESS_EVAL].info.is_ngg = false;
3512 stages[MESA_SHADER_VERTEX].info.is_ngg = false;
3518 * (this is checked later because we don't have the info here.)
3521 if (stages[MESA_SHADER_TESS_CTRL].nir && stages[MESA_SHADER_TESS_EVAL].info.is_ngg) {
3522 stages[MESA_SHADER_TESS_EVAL].info.is_ngg_passthrough = true;
3523 } else if (stages[MESA_SHADER_VERTEX].nir && stages[MESA_SHADER_VERTEX].info.is_ngg) {
3524 stages[MESA_SHADER_VERTEX].info.is_ngg_passthrough = true;
3547 stages[MESA_SHADER_VERTEX].info.vs.as_ls = true;
3552 stages[MESA_SHADER_TESS_EVAL].info.tes.as_es = true;
3554 stages[MESA_SHADER_VERTEX].info.vs.as_es = true;
3558 radv_nir_shader_info_init(&stages[MESA_SHADER_FRAGMENT].info);
3560 pipeline_key, &stages[MESA_SHADER_FRAGMENT].info);
3563 struct radv_shader_info *pre_ps_info = &stages[last_vgt_api_stage].info;
3575 bool ps_prim_id_in = stages[MESA_SHADER_FRAGMENT].info.ps.prim_id_input;
3576 bool ps_clip_dists_in = !!stages[MESA_SHADER_FRAGMENT].info.ps.num_input_clips_culls;
3592 radv_nir_shader_info_init(&stages[MESA_SHADER_TESS_CTRL].info);
3595 stages[MESA_SHADER_TESS_CTRL].info.vs.as_ls = true;
3599 &stages[MESA_SHADER_TESS_CTRL].info);
3612 radv_nir_shader_info_init(&stages[MESA_SHADER_GEOMETRY].info);
3616 stages[MESA_SHADER_GEOMETRY].info.vs.as_es = stages[MESA_SHADER_VERTEX].info.vs.as_es;
3618 stages[MESA_SHADER_GEOMETRY].info.tes.as_es = stages[MESA_SHADER_TESS_EVAL].info.tes.as_es;
3620 stages[MESA_SHADER_GEOMETRY].info.is_ngg = stages[pre_stage].info.is_ngg;
3621 stages[MESA_SHADER_GEOMETRY].info.gs.es_type = pre_stage;
3625 &stages[MESA_SHADER_GEOMETRY].info);
3635 radv_nir_shader_info_init(&stages[i].info);
3637 &stages[i].info);
3648 unsigned local_size = stages[MESA_SHADER_COMPUTE].nir->info.workgroup_size[0] *
3649 stages[MESA_SHADER_COMPUTE].nir->info.workgroup_size[1] *
3650 stages[MESA_SHADER_COMPUTE].nir->info.workgroup_size[2];
3656 stages[MESA_SHADER_COMPUTE].nir->info.cs.uses_wide_subgroup_intrinsics && !req_subgroup_size &&
3665 stages[MESA_SHADER_COMPUTE].info.cs.subgroup_size = subgroup_size;
3670 stages[i].info.wave_size = radv_get_wave_size(device, i, &stages[i].info);
3671 stages[i].info.ballot_bit_size = radv_get_ballot_bit_size(device, i, &stages[i].info);
3677 stages[MESA_SHADER_FRAGMENT].info.workgroup_size = stages[MESA_SHADER_FRAGMENT].info.wave_size;
3681 assert(!stages[MESA_SHADER_COMPUTE].nir->info.workgroup_size_variable);
3683 stages[MESA_SHADER_COMPUTE].info.workgroup_size =
3685 stages[MESA_SHADER_COMPUTE].nir->info.workgroup_size, false, UINT32_MAX);
3690 stages[MESA_SHADER_TASK].info.cs.uses_task_rings = true;
3691 stages[MESA_SHADER_MESH].info.cs.uses_task_rings = true;
3693 stages[MESA_SHADER_TASK].info.workgroup_size =
3695 stages[MESA_SHADER_TASK].nir->info.workgroup_size, false, UINT32_MAX);
3719 radv_declare_shader_args(gfx_level, pipeline_key, &stages[MESA_SHADER_TESS_CTRL].info,
3722 stages[MESA_SHADER_TESS_CTRL].info.user_sgprs_locs = stages[MESA_SHADER_TESS_CTRL].args.user_sgprs_locs;
3723 stages[MESA_SHADER_TESS_CTRL].info.inline_push_constant_mask =
3734 radv_declare_shader_args(gfx_level, pipeline_key, &stages[MESA_SHADER_GEOMETRY].info,
3737 stages[MESA_SHADER_GEOMETRY].info.user_sgprs_locs = stages[MESA_SHADER_GEOMETRY].args.user_sgprs_locs;
3738 stages[MESA_SHADER_GEOMETRY].info.inline_push_constant_mask =
3747 radv_declare_shader_args(gfx_level, pipeline_key, &stages[i].info, i, false,
3749 stages[i].info.user_sgprs_locs = stages[i].args.user_sgprs_locs;
3750 stages[i].info.inline_push_constant_mask = stages[i].args.ac.inline_push_const_mask;
3790 /* Copy the merged info back to the TCS */
3802 merge_tess_info(&stages[MESA_SHADER_TESS_EVAL].nir->info,
3803 &stages[MESA_SHADER_TESS_CTRL].nir->info);
3806 unsigned tess_out_patch_size = stages[MESA_SHADER_TESS_CTRL].nir->info.tess.tcs_vertices_out;
3811 stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_inputs,
3812 stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_outputs,
3813 stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_patch_outputs,
3820 stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_inputs, num_patches,
3821 stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_outputs,
3822 stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_patch_outputs);
3824 stages[MESA_SHADER_TESS_CTRL].info.num_tess_patches = num_patches;
3825 stages[MESA_SHADER_TESS_CTRL].info.tcs.num_lds_blocks = tcs_lds_size;
3826 stages[MESA_SHADER_TESS_CTRL].info.tcs.tes_reads_tess_factors =
3827 !!(stages[MESA_SHADER_TESS_EVAL].nir->info.inputs_read &
3829 stages[MESA_SHADER_TESS_CTRL].info.tcs.tes_inputs_read = stages[MESA_SHADER_TESS_EVAL].nir->info.inputs_read;
3830 stages[MESA_SHADER_TESS_CTRL].info.tcs.tes_patch_inputs_read =
3831 stages[MESA_SHADER_TESS_EVAL].nir->info.patch_inputs_read;
3833 stages[MESA_SHADER_TESS_EVAL].info.num_tess_patches = num_patches;
3834 stages[MESA_SHADER_GEOMETRY].info.num_tess_patches = num_patches;
3835 stages[MESA_SHADER_VERTEX].info.num_tess_patches = num_patches;
3836 stages[MESA_SHADER_TESS_CTRL].info.tcs.tcs_vertices_out = tess_out_patch_size;
3837 stages[MESA_SHADER_VERTEX].info.tcs.tcs_vertices_out = tess_out_patch_size;
3849 stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq =
3852 stages[MESA_SHADER_VERTEX].nir->info.float_controls_execution_mode ==
3853 stages[MESA_SHADER_TESS_CTRL].nir->info.float_controls_execution_mode;
3855 if (stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq)
3856 stages[MESA_SHADER_VERTEX].info.vs.tcs_temp_only_input_mask =
3857 stages[MESA_SHADER_TESS_CTRL].nir->info.inputs_read &
3858 stages[MESA_SHADER_VERTEX].nir->info.outputs_written &
3859 ~stages[MESA_SHADER_TESS_CTRL].nir->info.tess.tcs_cross_invocation_inputs_read &
3860 ~stages[MESA_SHADER_TESS_CTRL].nir->info.inputs_read_indirectly &
3861 ~stages[MESA_SHADER_VERTEX].nir->info.outputs_accessed_indirectly;
3864 stages[MESA_SHADER_TESS_CTRL].info.vs.tcs_in_out_eq = stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq;
3865 stages[MESA_SHADER_TESS_CTRL].info.vs.tcs_temp_only_input_mask =
3866 stages[MESA_SHADER_VERTEX].info.vs.tcs_temp_only_input_mask;
3870 stages[s].info.workgroup_size =
4138 if (last_vgt_shader->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_SHADING_RATE))
4148 BITSET_TEST(fs_shader->info.system_values_read, SYSTEM_VALUE_FRAG_COORD)) {
4318 if (enable_mrt_output_nan_fixup && !nir->info.internal && !is_16bit) {
4483 struct radv_shader_info info = {0};
4485 if (stages[MESA_SHADER_GEOMETRY].info.vs.outinfo.export_clip_dists)
4486 info.vs.outinfo.export_clip_dists = true;
4489 &info);
4490 info.wave_size = 64; /* Wave32 not supported. */
4491 info.workgroup_size = 64; /* HW VS: separate waves, no workgroups */
4492 info.ballot_bit_size = 64;
4497 radv_declare_shader_args(device->physical_device->rad_info.gfx_level, pipeline_key, &info,
4499 info.user_sgprs_locs = gs_copy_args.user_sgprs_locs;
4500 info.inline_push_constant_mask = gs_copy_args.ac.inline_push_const_mask;
4502 return radv_create_gs_copy_shader(device, stages[MESA_SHADER_GEOMETRY].nir, &info, &gs_copy_args,
4525 stages[last_vgt_api_stage].info.is_ngg;
4565 active_stages &= ~(1 << shaders[0]->info.stage);
4567 active_stages &= ~(1 << shaders[1]->info.stage);
4697 bool pipeline_has_ngg = (stages[MESA_SHADER_VERTEX].nir && stages[MESA_SHADER_VERTEX].info.is_ngg) ||
4698 (stages[MESA_SHADER_TESS_EVAL].nir && stages[MESA_SHADER_TESS_EVAL].info.is_ngg) ||
4699 (stages[MESA_SHADER_MESH].nir && stages[MESA_SHADER_MESH].info.is_ngg);
4722 /* Gather info again, information such as outputs_read can be out-of-date. */
4732 stages[MESA_SHADER_TESS_CTRL].nir->info.tess.tcs_vertices_out, NULL);
4751 ngg_info = &stages[MESA_SHADER_GEOMETRY].info.ngg_info;
4753 ngg_info = &stages[MESA_SHADER_TESS_EVAL].info.ngg_info;
4755 ngg_info = &stages[MESA_SHADER_VERTEX].info.ngg_info;
4757 ngg_info = &stages[MESA_SHADER_MESH].info.ngg_info;
4766 struct gfx9_gs_info *gs_info = &stages[MESA_SHADER_GEOMETRY].info.gs_ring_info;
4772 stages[hw_vs_api_stage].info.workgroup_size = stages[hw_vs_api_stage].info.wave_size;
4789 assert(stages[i].info.wave_size && stages[i].info.workgroup_size);
4825 /* Gather info again, to update whether 8/16-bit are used. */
4829 struct radv_shader_info *info = &stages[i].info;
4832 info = &stages[MESA_SHADER_TESS_CTRL].info;
4834 info = &stages[MESA_SHADER_GEOMETRY].info;
4836 info = &stages[MESA_SHADER_GEOMETRY].info;
4839 NIR_PASS_V(stages[i].nir, radv_nir_apply_pipeline_layout, device, pipeline_layout, info,
4873 &stages[i].info, &stages[i].args, pipeline_key,
4878 if (stages[i].nir->info.bit_sizes_int & (8 | 16)) {
4891 if (((stages[i].nir->info.bit_sizes_int | stages[i].nir->info.bit_sizes_float) & 16) &&
5080 const struct radv_graphics_pipeline_info *info)
5304 for (unsigned i = 0; i < info->ri.color_att_count; i++) {
5305 if (!info->cb.att[i].color_write_mask)
5308 if (info->ri.color_att_formats[i] == VK_FORMAT_UNDEFINED)
5311 color_bytes_per_pixel += vk_format_get_blocksize(info->ri.color_att_formats[i]);
5325 if (radv_pipeline_has_ds_attachments(&info->ri)) {
5327 unsigned depth_coeff = info->ri.depth_att_format != VK_FORMAT_UNDEFINED ? 5 : 0;
5328 unsigned stencil_coeff = info->ri.stencil_att_format != VK_FORMAT_UNDEFINED ? 1 : 0;
5344 const struct radv_graphics_pipeline_info *info)
5372 for (unsigned i = 0; i < info->ri.color_att_count; i++) {
5373 if (!info->cb.att[i].color_write_mask)
5376 if (info->ri.color_att_formats[i] == VK_FORMAT_UNDEFINED)
5379 color_bytes_per_pixel += vk_format_get_blocksize(info->ri.color_att_formats[i]);
5406 if (radv_pipeline_has_ds_attachments(&info->ri)) {
5408 unsigned depth_coeff = info->ri.depth_att_format != VK_FORMAT_UNDEFINED ? 5 : 0;
5409 unsigned stencil_coeff = info->ri.stencil_att_format != VK_FORMAT_UNDEFINED ? 1 : 0;
5429 const struct radv_graphics_pipeline_info *info)
5438 for (unsigned i = 0; i < info->ri.color_att_count; i++) {
5439 if (!info->cb.att[i].color_write_mask)
5442 if (info->ri.color_att_formats[i] == VK_FORMAT_UNDEFINED)
5445 unsigned bytes = vk_format_get_blocksize(info->ri.color_att_formats[i]);
5490 const struct radv_graphics_pipeline_info *info)
5499 bin_size = radv_gfx10_compute_bin_size(pipeline, info);
5501 bin_size = radv_gfx9_compute_bin_size(pipeline, info);
5520 radv_pipeline_init_disabled_binning_state(pipeline, info);
5559 const struct radv_graphics_pipeline_info *info)
5562 const VkConservativeRasterizationModeEXT mode = info->rs.conservative_mode;
5636 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out, pdevice->rad_info.gfx_level);
5637 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
5743 unsigned num_lds_blocks = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks;
5769 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
5785 bool es_enable_prim_id = outinfo->export_prim_id || (es && es->info.uses_prim_id);
5792 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
5843 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
5895 ac_compute_late_alloc(&pdevice->rad_info, true, shader->info.has_ngg_culling,
5923 if (shader->info.has_ngg_culling) {
5974 if (vs->info.vs.as_ls)
5976 else if (vs->info.vs.as_es)
5978 else if (vs->info.is_ngg)
5995 if (tes->info.is_ngg) {
5997 } else if (tes->info.tes.as_es)
6016 const struct radv_graphics_pipeline_info *info)
6024 num_tcs_input_cp = info->ts.patch_control_points;
6026 pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; // TCS VERTICES OUT
6027 num_patches = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
6038 switch (tes->info.tes._primitive_mode) {
6052 switch (tes->info.tes.spacing) {
6066 bool ccw = tes->info.tes.ccw;
6067 if (info->ts.domain_origin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
6070 if (tes->info.tes.point_mode)
6072 else if (tes->info.tes._primitive_mode == TESS_PRIMITIVE_ISOLINES)
6098 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
6105 gs_max_out_vertices = gs->info.gs.vertices_out;
6106 max_stream = gs->info.gs.max_stream;
6107 num_components = gs->info.gs.num_stream_output_components;
6129 uint32_t gs_num_invocations = gs->info.gs.invocations;
6195 if (gs->info.is_ngg)
6200 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
6213 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, ms->info.workgroup_size);
6276 bool flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << *ps_offset));
6277 bool explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << *ps_offset));
6278 bool float16 = !!(ps->info.ps.float16_shaded_mask & (1u << *ps_offset));
6296 if (ps->info.ps.prim_id_input && !mesh)
6300 if (ps->info.ps.layer_input && !mesh)
6304 if (ps->info.ps.viewport_index_input && !mesh)
6308 if (ps->info.ps.has_pcoord)
6311 if (ps->info.ps.num_input_clips_culls) {
6315 if (ps->info.ps.num_input_clips_culls > 4)
6320 input_mask_to_ps_inputs(outinfo, ps, ps->info.ps.input_mask,
6325 if (ps->info.ps.prim_id_input && mesh)
6329 if (ps->info.ps.layer_input && mesh)
6333 if (ps->info.ps.viewport_index_input && mesh)
6337 input_mask_to_ps_inputs(outinfo, ps, ps->info.ps.input_per_primitive_mask,
6355 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
6360 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
6362 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
6371 bool mask_export_enable = ps->info.ps.writes_sample_mask;
6373 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
6374 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
6375 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
6378 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
6379 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
6380 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
6381 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
6413 !ps->info.ps.num_interp && ps->config.lds_size;
6417 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
6418 S_0286D8_NUM_PRIM_INTERP(ps->info.ps.num_prim_interp) |
6419 S_0286D8_PS_W32_EN(ps->info.wave_size == 32) |
6426 ac_get_spi_shader_z_format(ps->info.ps.writes_z, ps->info.ps.writes_stencil,
6427 ps->info.ps.writes_sample_mask, false));
6441 radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.tes.spacing ==
6470 if (pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.needs_ms_scratch_ring)
6496 hs_size = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
6499 vs_size = gs_size = pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
6501 vs_size = pipeline->base.gs_copy_shader->info.wave_size;
6503 vs_size = pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
6505 vs_size = pipeline->base.shaders[MESA_SHADER_VERTEX]->info.wave_size;
6507 vs_size = gs_size = pipeline->base.shaders[MESA_SHADER_MESH]->info.wave_size;
6525 const struct radv_graphics_pipeline_info *info)
6529 if (!info->dr.count) {
6538 unsigned relevant_subset = i & ((1u << info->dr.count) - 1);
6540 if (info->dr.mode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT && !relevant_subset)
6543 if (info->dr.mode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT && relevant_subset)
6562 primgroup_size = pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
6565 &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
6573 if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
6574 radv_get_shader(&pipeline->base, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
6602 const struct radv_graphics_pipeline_info *info)
6606 bool enable_vrs = radv_is_vrs_enabled(pipeline, info);
6631 if (!ps->info.ps.allow_flat_shading)
6640 const struct radv_graphics_pipeline_info *info)
6645 bool enable_vrs = radv_is_vrs_enabled(pipeline, info);
6653 } else if (!radv_is_static_vrs_enabled(pipeline, info) && pipeline->force_vrs_per_vertex &&
6668 mode = ps->info.ps.can_discard ? V_028064_VRS_COMB_MODE_MIN : V_028064_VRS_COMB_MODE_PASSTHRU;
6688 const struct radv_graphics_pipeline_info *info)
6701 radv_pipeline_emit_raster_state(ctx_cs, pipeline, info);
6709 radv_pipeline_emit_tess_state(ctx_cs, pipeline, info);
6717 radv_pipeline_emit_cliprect_rule(ctx_cs, info);
6724 gfx103_pipeline_emit_vgt_draw_payload_cntl(ctx_cs, pipeline, info);
6725 gfx103_pipeline_emit_vrs_state(ctx_cs, pipeline, info);
6736 const struct radv_graphics_pipeline_info *info)
6739 const struct radv_shader_info *vs_info = &radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX)->info;
6742 pipeline->attrib_ends[i] = info->vi.attrib_ends[i];
6743 pipeline->attrib_index_offset[i] = info->vi.attrib_index_offset[i];
6744 pipeline->attrib_bindings[i] = info->vi.attrib_bindings[i];
6748 pipeline->binding_stride[i] = info->vi.binding_stride[i];
6761 pipeline->can_use_simple_input = vs_shader->info.is_ngg == pdevice->use_ngg &&
6762 vs_shader->info.wave_size == pdevice->ge_wave_size;
6781 if (shader && shader->info.so.num_outputs > 0)
6804 /* We need this info for some stages even when the shader doesn't exist. */
6824 radv_get_shader(&pipeline->base, first_stage)->info.vs.needs_draw_id;
6826 radv_get_shader(&pipeline->base, first_stage)->info.vs.needs_base_instance;
6834 const struct radv_graphics_pipeline_info *info)
6840 si_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
6842 if (pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) {
6846 pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes._primitive_mode);
6850 si_conv_gl_prim_to_gs_out(pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.output_prim);
6852 gs_out = si_conv_prim_to_gs_out(info->ia.primitive_topology);
6863 const struct radv_graphics_pipeline_info *info,
6894 if (radv_pipeline_has_ds_attachments(&info->ri)) {
6940 struct radv_graphics_pipeline_info info = radv_pipeline_init_graphics_info(pipeline, pCreateInfo);
6942 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, &info);
6948 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &info, &blend);
6958 uint32_t vgt_gs_out_prim_type = radv_pipeline_init_vgt_gs_out(pipeline, &info);
6960 radv_pipeline_init_multisample_state(pipeline, &blend, &info, vgt_gs_out_prim_type);
6963 radv_pipeline_init_input_assembly_state(pipeline, &info);
6964 radv_pipeline_init_dynamic_state(pipeline, &info);
6966 pipeline->negative_one_to_one = info.vp.negative_one_to_one;
6968 radv_pipeline_init_raster_state(pipeline, &info);
6971 radv_pipeline_init_depth_stencil_state(pipeline, &info);
6974 gfx103_pipeline_init_vrs_state(pipeline, &info);
6992 if ((device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard) &&
6994 if (!ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask)
7004 radv_pipeline_init_gs_ring_state(pipeline, &gs->info.gs_ring_info);
7008 pipeline->tess_patch_control_points = info.ts.patch_control_points;
7012 radv_pipeline_init_vertex_input_state(pipeline, &info);
7014 radv_pipeline_init_binning_state(pipeline, &blend, &info);
7024 pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.has_ngg_culling;
7026 pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.force_vrs_per_vertex;
7027 pipeline->uses_user_sample_locations = info.ms.sample_locs_enable;
7031 pipeline->line_width = info.rs.line_width;
7038 radv_pipeline_init_extra(pipeline, extra, &blend, &ds_state, &info, &vgt_gs_out_prim_type);
7041 radv_pipeline_emit_pm4(pipeline, &blend, &ds_state, vgt_gs_out_prim_type, &info);
7194 shader->info.cs.block_size[0] * shader->info.cs.block_size[1] * shader->info.cs.block_size[2];
7195 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup, shader->info.wave_size);
7206 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[0]));
7207 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[1]));
7208 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[2]));
7299 unsigned *cs_block_size = compute_shader->info.cs.block_size;
7466 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
7588 const struct aco_compiler_statistic_info *info = &aco_statistic_infos[i];
7590 desc_copy(s->name, info->name);
7591 desc_copy(s->description, info->desc);