Lines Matching defs:ds_state
2204 struct radv_depth_stencil_state ds_state = {0};
2212 ds_state.db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(info->ms.raster_samples > 2);
2215 ds_state.db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE(1);
2229 ds_state.db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2233 ds_state.db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2258 ds_state.db_render_control |= S_028000_OREO_MODE(V_028000_OMODE_O_THEN_B) |
2264 return ds_state;
5525 const struct radv_depth_stencil_state *ds_state)
5527 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, ds_state->db_render_control);
5530 radeon_emit(ctx_cs, ds_state->db_render_override);
5531 radeon_emit(ctx_cs, ds_state->db_render_override2);
6686 const struct radv_depth_stencil_state *ds_state,
6699 radv_pipeline_emit_depth_stencil_state(ctx_cs, ds_state);
6862 struct radv_depth_stencil_state *ds_state,
6895 ds_state->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
6896 ds_state->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
6897 ds_state->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
6898 ds_state->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
6899 ds_state->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
6970 struct radv_depth_stencil_state ds_state =
7038 radv_pipeline_init_extra(pipeline, extra, &blend, &ds_state, &info, &vgt_gs_out_prim_type);
7041 radv_pipeline_emit_pm4(pipeline, &blend, &ds_state, vgt_gs_out_prim_type, &info);