Lines Matching defs:device
160 radv_pipeline_slab_create(struct radv_device *device, struct radv_pipeline *pipeline,
171 slab->alloc = radv_alloc_shader_memory(device, code_size, pipeline);
181 radv_pipeline_slab_destroy(struct radv_device *device, struct radv_pipeline_slab *slab)
186 radv_free_shader_memory(device, slab->alloc);
191 radv_pipeline_destroy(struct radv_device *device, struct radv_pipeline *pipeline,
216 radv_pipeline_slab_destroy(device, pipeline->slab);
220 radv_shader_destroy(device, pipeline->shaders[i]);
223 radv_shader_destroy(device, pipeline->gs_copy_shader);
229 vk_free2(&device->vk.alloc, allocator, pipeline);
236 RADV_FROM_HANDLE(radv_device, device, _device);
242 radv_pipeline_destroy(device, pipeline, pAllocator);
246 radv_get_hash_flags(const struct radv_device *device, bool stats)
250 if (device->physical_device->use_ngg_culling)
252 if (device->instance->perftest_flags & RADV_PERFTEST_EMULATE_RT)
254 if (device->physical_device->rt_wave_size == 64)
256 if (device->physical_device->cs_wave_size == 32)
258 if (device->physical_device->ps_wave_size == 32)
260 if (device->physical_device->ge_wave_size == 32)
262 if (device->physical_device->use_llvm)
266 if (device->robust_buffer_access) /* forces per-attribute vertex descriptors */
268 if (device->robust_buffer_access2) /* affects load/store vectorizer */
270 if (device->instance->debug_flags & RADV_DEBUG_SPLIT_FMA)
276 radv_pipeline_init_scratch(const struct radv_device *device, struct radv_pipeline *pipeline)
283 unsigned max_stage_waves = device->scratch_waves;
289 MIN2(max_stage_waves, 4 * device->physical_device->rad_info.num_cu *
290 radv_get_max_waves(device, pipeline->shaders[i], i));
473 radv_choose_spi_color_format(const struct radv_device *device, VkFormat vk_format,
477 bool use_rbplus = device->physical_device->rad_info.rbplus_allowed;
549 cf = radv_choose_spi_color_format(pipeline->base.device, fmt, blend_enable,
616 radv_format_meta_fs_key(struct radv_device *device, VkFormat format)
618 unsigned col_format = radv_choose_spi_color_format(device, format, false, false);
697 const struct radv_device *device = pipeline->base.device;
700 const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
708 if (device->instance->debug_flags & RADV_DEBUG_NO_ATOC_DITHERING)
840 if (device->physical_device->rad_info.has_rbplus) {
853 (device->physical_device->rad_info.gfx_level >= GFX11 && blend.blend_enable_4bit))
986 if (!pipeline->base.device->physical_device->out_of_order_rast_allowed)
1079 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1403 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1498 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
1839 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
2154 const struct radv_device *device = pipeline->base.device;
2168 if (device->physical_device->rad_info.gfx_level >= GFX10) {
2191 device->vk.enabled_extensions.EXT_depth_range_unrestricted) {
2203 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
2271 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
2488 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
2717 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
2939 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
3197 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
3285 struct radv_device *device = pipeline->device;
3293 key.disable_aniso_single_level = device->instance->disable_aniso_single_level &&
3294 device->physical_device->rad_info.gfx_level < GFX8;
3296 key.image_2d_view_of_3d = device->image_2d_view_of_3d &&
3297 device->physical_device->rad_info.gfx_level == GFX9;
3308 struct radv_device *device = pipeline->base.device;
3345 if (device->physical_device->rad_info.gfx_level < GFX8) {
3349 if (device->physical_device->rad_info.gfx_level >= GFX11) {
3355 if (device->physical_device->rad_info.gfx_level >= GFX10) {
3359 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
3362 if (device->instance->enable_mrt_output_nan_fixup)
3366 key.ps.force_vrs_enabled = device->force_vrs_enabled;
3368 if (device->instance->debug_flags & RADV_DEBUG_INVARIANT_GEOM)
3371 key.use_ngg = device->physical_device->use_ngg;
3373 if ((radv_is_vrs_enabled(pipeline, info) || device->force_vrs_enabled) &&
3374 (device->physical_device->rad_info.family == CHIP_NAVI21 ||
3375 device->physical_device->rad_info.family == CHIP_NAVI22 ||
3376 device->physical_device->rad_info.family == CHIP_VANGOGH))
3379 if (device->instance->disable_sinking_load_input_fs)
3382 if (device->primitives_generated_query)
3391 radv_get_wave_size(struct radv_device *device, gl_shader_stage stage,
3399 return device->physical_device->ps_wave_size;
3401 return device->physical_device->cs_wave_size;
3403 return device->physical_device->ge_wave_size;
3407 radv_get_ballot_bit_size(struct radv_device *device, gl_shader_stage stage,
3421 const struct radv_physical_device *pdevice = pipeline->device->physical_device;
3438 !radv_use_llvm_for_stage(pipeline->device, es_stage);
3469 struct radv_device *device = pipeline->device;
3492 assert(device->physical_device->rad_info.gfx_level < GFX11);
3505 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
3507 assert(device->physical_device->rad_info.gfx_level < GFX11);
3537 struct radv_device *device = pipeline->device;
3559 radv_nir_shader_info_pass(device, stages[MESA_SHADER_FRAGMENT].nir, pipeline_layout,
3588 if (device->physical_device->rad_info.gfx_level >= GFX9 &&
3598 radv_nir_shader_info_pass(device, combined_nir[i], pipeline_layout, pipeline_key,
3606 if (device->physical_device->rad_info.gfx_level >= GFX9 &&
3624 radv_nir_shader_info_pass(device, combined_nir[i], pipeline_layout, pipeline_key,
3636 radv_nir_shader_info_pass(device, stages[i].nir, pipeline_layout, pipeline_key,
3646 subgroup_size = device->physical_device->cs_wave_size;
3655 if (device->physical_device->cs_wave_size == 32 &&
3670 stages[i].info.wave_size = radv_get_wave_size(device, i, &stages[i].info);
3671 stages[i].info.ballot_bit_size = radv_get_ballot_bit_size(device, i, &stages[i].info);
3700 radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stage *stages,
3703 enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
3713 stages[i].args.explicit_scratch_args = !radv_use_llvm_for_stage(device, i);
3714 stages[i].args.remap_spi_ps_input = !radv_use_llvm_for_stage(device, i);
3715 stages[i].args.load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr;
3799 gather_tess_info(struct radv_device *device, struct radv_pipeline_stage *stages,
3814 device->physical_device->hs.tess_offchip_block_dw_size, device->physical_device->rad_info.gfx_level,
3815 device->physical_device->rad_info.family);
3819 device->physical_device->rad_info.gfx_level, tess_in_patch_size, tess_out_patch_size,
3839 if (!radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX)) {
3850 device->physical_device->rad_info.gfx_level >= GFX9 &&
3871 ac_compute_lshs_workgroup_size(device->physical_device->rad_info.gfx_level, s, num_patches,
3942 struct radv_device *device = _;
3943 enum amd_gfx_level chip = device->physical_device->rad_info.gfx_level;
4013 const struct radv_device *device = _;
4014 enum amd_gfx_level chip = device->physical_device->rad_info.gfx_level;
4067 radv_upload_shaders(struct radv_device *device, struct radv_pipeline *pipeline,
4086 pipeline->slab = radv_pipeline_slab_create(device, pipeline, code_size);
4105 if (!radv_shader_binary_upload(device, binaries[i], shader, dest_ptr))
4115 if (!radv_shader_binary_upload(device, gs_copy_binary, pipeline->gs_copy_shader, dest_ptr))
4127 struct radv_device *device = pipeline->device;
4129 if (!device->force_vrs_enabled)
4482 struct radv_device *device = pipeline->device;
4488 radv_nir_shader_info_pass(device, stages[MESA_SHADER_GEOMETRY].nir, pipeline_layout, pipeline_key,
4496 gs_copy_args.explicit_scratch_args = !radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX);
4497 radv_declare_shader_args(device->physical_device->rad_info.gfx_level, pipeline_key, &info,
4502 return radv_create_gs_copy_shader(device, stages[MESA_SHADER_GEOMETRY].nir, &info, &gs_copy_args,
4516 struct radv_device *device = pipeline->device;
4542 if (device->physical_device->rad_info.gfx_level >= GFX9 &&
4559 pipeline->shaders[s] = radv_shader_nir_to_asm(device, &stages[s], shaders, shader_count,
4573 struct radv_device *device, struct radv_pipeline_cache *cache,
4589 device->keep_shader_info;
4591 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
4592 device->keep_shader_info;
4634 radv_get_hash_flags(device, keep_statistic_info));
4641 radv_create_shaders_from_pipeline_cache(device, cache, hash, pipeline,
4658 nir_builder fs_b = radv_meta_init_shader(device, MESA_SHADER_FRAGMENT, "noop_fs");
4678 stages[s].nir = radv_shader_spirv_to_nir(device, &stages[s], pipeline_key);
4689 NIR_PASS(_, last_vgt_shader, radv_force_primitive_shading_rate, device);
4724 radv_lower_io(device, stages[i].nir, stages[MESA_SHADER_MESH].nir);
4733 gather_tess_info(device, stages, pipeline_key);
4740 if (stages[MESA_SHADER_FRAGMENT].nir && !radv_use_llvm_for_stage(device, MESA_SHADER_FRAGMENT)) {
4777 radv_declare_pipeline_args(device, stages, pipeline_key);
4791 if (!radv_use_llvm_for_stage(device, i)) {
4810 .has_shared2_amd = device->physical_device->rad_info.gfx_level >= GFX7,
4813 if (device->robust_buffer_access2) {
4823 !device->instance->disable_shrink_image_store);
4830 if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) {
4839 NIR_PASS_V(stages[i].nir, radv_nir_apply_pipeline_layout, device, pipeline_layout, info,
4844 NIR_PASS(_, stages[i].nir, nir_lower_alu_width, opt_vectorize_callback, device);
4854 .allow_fp16 = device->physical_device->rad_info.gfx_level >= GFX9,
4866 bool io_to_mem = radv_lower_io_to_mem(device, &stages[i], pipeline_key);
4869 radv_lower_ngg(device, &stages[i], pipeline_key);
4872 NIR_PASS_V(stages[i].nir, radv_nir_lower_abi, device->physical_device->rad_info.gfx_level,
4874 radv_use_llvm_for_stage(device, i));
4879 if (device->physical_device->rad_info.gfx_level >= GFX8) {
4884 if (nir_lower_bit_size(stages[i].nir, lower_bit_size_callback, device)) {
4888 if (device->physical_device->rad_info.gfx_level >= GFX8)
4892 device->physical_device->rad_info.gfx_level >= GFX9) {
4893 bool separate_g16 = device->physical_device->rad_info.gfx_level >= GFX10;
4917 NIR_PASS(_, stages[i].nir, nir_opt_vectorize, opt_vectorize_callback, device);
4921 NIR_PASS(_, stages[i].nir, nir_lower_alu_width, opt_vectorize_callback, device);
4939 if (radv_can_dump_shader(device, stages[i].nir, false))
4964 radv_upload_shaders(device, pipeline, binaries, gs_copy_binary);
4973 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline, binaries,
4988 if (radv_can_dump_shader_stats(device, stages[i].nir) && pipeline->shaders[i]) {
4989 radv_dump_shader_stats(device, pipeline, i, stderr);
5082 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5346 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5431 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5492 const struct radv_device *device = pipeline->base.device;
5494 if (device->physical_device->rad_info.gfx_level < GFX9)
5498 if (device->physical_device->rad_info.gfx_level >= GFX10) {
5500 } else if (device->physical_device->rad_info.gfx_level == GFX9) {
5505 if (device->pbb_allowed && bin_size.width && bin_size.height) {
5506 struct radv_binning_settings settings = radv_get_binning_settings(device->physical_device);
5539 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5561 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5594 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5622 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5650 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5742 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5763 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5941 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
5988 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6018 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6097 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6207 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6389 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6434 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6453 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6590 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6626 struct radv_device *device = pipeline->base.device;
6628 if (device->instance->debug_flags & RADV_DEBUG_NO_VRS_FLAT_SHADING)
6642 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6690 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6738 const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
6799 struct radv_device *device = pipeline->base.device;
6806 pipeline, i, device->physical_device->rad_info.gfx_level);
6904 radv_pipeline_init(struct radv_device *device, struct radv_pipeline *pipeline,
6907 vk_object_base_init(&device->vk, &pipeline->base, VK_OBJECT_TYPE_PIPELINE);
6909 pipeline->device = device;
6914 radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv_device *device,
6950 result = radv_create_shaders(&pipeline->base, pipeline_layout, device, cache, &key, pCreateInfo->pStages,
6973 if (device->physical_device->rad_info.gfx_level >= GFX10_3)
6992 if ((device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard) &&
7016 radv_pipeline_init_scratch(device, &pipeline->base);
7053 RADV_FROM_HANDLE(radv_device, device, _device);
7058 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
7061 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
7063 radv_pipeline_init(device, &pipeline->base, RADV_PIPELINE_GRAPHICS);
7065 result = radv_graphics_pipeline_init(pipeline, device, cache, pCreateInfo, extra);
7067 radv_pipeline_destroy(device, &pipeline->base, pAllocator);
7214 struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
7256 RADV_FROM_HANDLE(radv_device, device, _device);
7262 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
7266 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
7269 radv_pipeline_init(device, &pipeline->base, RADV_PIPELINE_COMPUTE);
7280 result = radv_create_shaders(&pipeline->base, pipeline_layout, device, cache, &key, &pCreateInfo->stage,
7285 radv_pipeline_destroy(device, &pipeline->base, pAllocator);
7292 radv_pipeline_init_scratch(device, &pipeline->base);
7297 if (device->physical_device->rad_info.has_cs_regalloc_hang_bug) {
7498 RADV_FROM_HANDLE(radv_device, device, _device);
7504 const struct radv_physical_device *pdevice = device->physical_device;
7508 unsigned max_waves = radv_get_max_waves(device, shader, stage);
7635 RADV_FROM_HANDLE(radv_device, device, _device);
7658 if (radv_use_llvm_for_stage(device, stage)) {