Lines Matching refs:CTR
162 #define CTR(block, ctr) (S_REG_BLOCK(block) | S_REG_SEL(ctr))
165 enum { GRBM_PERF_SEL_GUI_ACTIVE = CTR(GRBM, 2) };
167 enum { CPF_PERF_SEL_CPF_STAT_BUSY_GFX10 = CTR(CPF, 0x18) };
170 GL1C_PERF_SEL_REQ = CTR(GL1C, 0xe),
171 GL1C_PERF_SEL_REQ_MISS = CTR(GL1C, 0x12),
175 GL2C_PERF_SEL_REQ = CTR(GL2C, 0x3),
177 GL2C_PERF_SEL_MISS_GFX101 = CTR(GL2C, 0x23),
178 GL2C_PERF_SEL_MC_WRREQ_GFX101 = CTR(GL2C, 0x4b),
179 GL2C_PERF_SEL_EA_WRREQ_64B_GFX101 = CTR(GL2C, 0x4c),
180 GL2C_PERF_SEL_EA_RDREQ_32B_GFX101 = CTR(GL2C, 0x59),
181 GL2C_PERF_SEL_EA_RDREQ_64B_GFX101 = CTR(GL2C, 0x5a),
182 GL2C_PERF_SEL_EA_RDREQ_96B_GFX101 = CTR(GL2C, 0x5b),
183 GL2C_PERF_SEL_EA_RDREQ_128B_GFX101 = CTR(GL2C, 0x5c),
185 GL2C_PERF_SEL_MISS_GFX103 = CTR(GL2C, 0x2b),
186 GL2C_PERF_SEL_MC_WRREQ_GFX103 = CTR(GL2C, 0x53),
187 GL2C_PERF_SEL_EA_WRREQ_64B_GFX103 = CTR(GL2C, 0x55),
188 GL2C_PERF_SEL_EA_RDREQ_32B_GFX103 = CTR(GL2C, 0x63),
189 GL2C_PERF_SEL_EA_RDREQ_64B_GFX103 = CTR(GL2C, 0x64),
190 GL2C_PERF_SEL_EA_RDREQ_96B_GFX103 = CTR(GL2C, 0x65),
191 GL2C_PERF_SEL_EA_RDREQ_128B_GFX103 = CTR(GL2C, 0x66),
195 SQ_PERF_SEL_WAVES = CTR(SQ, 0x4),
196 SQ_PERF_SEL_INSTS_ALL_GFX10 = CTR(SQ, 0x31),
197 SQ_PERF_SEL_INSTS_GDS_GFX10 = CTR(SQ, 0x37),
198 SQ_PERF_SEL_INSTS_LDS_GFX10 = CTR(SQ, 0x3b),
199 SQ_PERF_SEL_INSTS_SALU_GFX10 = CTR(SQ, 0x3c),
200 SQ_PERF_SEL_INSTS_SMEM_GFX10 = CTR(SQ, 0x3d),
201 SQ_PERF_SEL_INSTS_VALU_GFX10 = CTR(SQ, 0x40),
202 SQ_PERF_SEL_INSTS_TEX_LOAD_GFX10 = CTR(SQ, 0x45),
203 SQ_PERF_SEL_INSTS_TEX_STORE_GFX10 = CTR(SQ, 0x46),
204 SQ_PERF_SEL_INST_CYCLES_VALU_GFX10 = CTR(SQ, 0x75),
208 TCP_PERF_SEL_REQ_GFX10 = CTR(TCP, 0x9),
209 TCP_PERF_SEL_REQ_MISS_GFX10 = CTR(TCP, 0x12),