Lines Matching defs:cmd_buffer
467 radv_emit_instance(struct radv_cmd_buffer *cmd_buffer, int se, int instance)
469 struct radeon_cmdbuf *cs = cmd_buffer->cs;
488 radv_emit_select(struct radv_cmd_buffer *cmd_buffer, struct ac_pc_block *block, unsigned count,
492 struct radeon_cmdbuf *cs = cmd_buffer->cs;
502 radeon_set_perfctr_reg(cmd_buffer, regs->select0[idx],
513 radv_pc_emit_block_instance_read(struct radv_cmd_buffer *cmd_buffer, struct ac_pc_block *block,
517 struct radeon_cmdbuf *cs = cmd_buffer->cs;
535 radv_pc_get_num_instances(cmd_buffer->device->physical_device, block);
541 radv_pc_sample_block(struct radv_cmd_buffer *cmd_buffer, struct ac_pc_block *block, unsigned count,
546 se_end = cmd_buffer->device->physical_device->rad_info.max_se;
550 radv_emit_instance(cmd_buffer, se, instance);
551 radv_pc_emit_block_instance_read(cmd_buffer, block, count, va);
558 radv_pc_wait_idle(struct radv_cmd_buffer *cmd_buffer)
560 struct radeon_cmdbuf *cs = cmd_buffer->cs;
579 radv_pc_stop_and_sample(struct radv_cmd_buffer *cmd_buffer, struct radv_pc_query_pool *pool,
582 struct radeon_cmdbuf *cs = cmd_buffer->cs;
583 struct radv_physical_device *pdevice = cmd_buffer->device->physical_device;
588 radv_pc_wait_idle(cmd_buffer);
590 radv_emit_instance(cmd_buffer, -1, -1);
591 radv_emit_windowed_counters(cmd_buffer->device, cs, cmd_buffer->qf, false);
598 uint64_t pred_va = radv_buffer_get_va(cmd_buffer->device->perf_counter_bo) +
622 radv_pc_sample_block(cmd_buffer, ac_block, pass_reg_cnt,
643 radv_emit_instance(cmd_buffer, -1, -1);
647 radv_pc_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_pc_query_pool *pool,
650 struct radeon_cmdbuf *cs = cmd_buffer->cs;
651 struct radv_physical_device *pdevice = cmd_buffer->device->physical_device;
654 cmd_buffer->state.uses_perf_counters = true;
656 cdw_max = radeon_check_space(cmd_buffer->device->ws, cs,
661 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pool->b.bo);
662 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->device->perf_counter_bo);
665 radv_buffer_get_va(cmd_buffer->device->perf_counter_bo) + PERF_CTR_BO_FENCE_OFFSET;
672 radv_pc_wait_idle(cmd_buffer);
677 radv_emit_inhibit_clockgating(cmd_buffer->device, cs, true);
678 radv_emit_spi_config_cntl(cmd_buffer->device, cs, true);
682 uint64_t pred_va = radv_buffer_get_va(cmd_buffer->device->perf_counter_bo) +
704 radv_emit_select(cmd_buffer, ac_block, pass_reg_cnt, pool->pc_regs + i + offset);
713 radv_emit_instance(cmd_buffer, -1, -1);
717 radv_pc_stop_and_sample(cmd_buffer, pool, va, false);
722 radv_emit_windowed_counters(cmd_buffer->device, cs, cmd_buffer->qf, true);
724 assert(cmd_buffer->cs->cdw <= cdw_max);
728 radv_pc_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_pc_query_pool *pool, uint64_t va)
730 struct radeon_cmdbuf *cs = cmd_buffer->cs;
734 radeon_check_space(cmd_buffer->device->ws, cs,
739 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pool->b.bo);
740 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->device->perf_counter_bo);
743 radv_buffer_get_va(cmd_buffer->device->perf_counter_bo) + PERF_CTR_BO_FENCE_OFFSET;
744 si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
745 radv_cmd_buffer_uses_mec(cmd_buffer), V_028A90_BOTTOM_OF_PIPE_TS, 0,
747 cmd_buffer->gfx9_fence_va);
750 radv_pc_wait_idle(cmd_buffer);
751 radv_pc_stop_and_sample(cmd_buffer, pool, va, true);
755 radv_emit_spi_config_cntl(cmd_buffer->device, cs, false);
756 radv_emit_inhibit_clockgating(cmd_buffer->device, cs, false);
758 assert(cmd_buffer->cs->cdw <= cdw_max);