Lines Matching defs:image
358 radv_get_depth_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
362 uint32_t samples = image->info.samples;
399 radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
406 width = radv_minify(image->info.width, range->baseMipLevel + level);
407 height = radv_minify(image->info.height, range->baseMipLevel + level);
412 .image = radv_image_to_handle(image),
413 .viewType = radv_meta_get_view_type(image),
414 .format = image->vk.format,
463 radv_process_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
475 pipeline = radv_get_depth_pipeline(cmd_buffer, image, subresourceRange, op);
481 assert(image->vk.create_flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT);
496 for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); ++l) {
499 if (!radv_htile_enabled(image, subresourceRange->baseMipLevel + l))
502 uint32_t width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l);
503 uint32_t height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l);
519 for (uint32_t s = 0; s < radv_get_layerCount(image, subresourceRange); s++) {
520 radv_process_depth_image_layer(cmd_buffer, image, subresourceRange, l, s);
528 radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
536 assert(radv_image_is_tc_compat_htile(image));
539 radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
547 for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); l++) {
551 if (!radv_htile_enabled(image, subresourceRange->baseMipLevel + l))
554 width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l);
555 height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l);
557 for (uint32_t s = 0; s < radv_get_layerCount(image, subresourceRange); s++) {
562 .image = radv_image_to_handle(image),
564 .format = image->vk.format,
576 .image = radv_image_to_handle(image),
578 .format = image->vk.format,
628 radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
631 uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, image);
633 cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, image, subresourceRange, htile_value);
637 radv_expand_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
647 radv_process_depth_stencil(cmd_buffer, image, subresourceRange, sample_locs, DEPTH_DECOMPRESS);
649 radv_expand_depth_stencil_compute(cmd_buffer, image, subresourceRange);
654 radv_resummarize_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
664 radv_process_depth_stencil(cmd_buffer, image, subresourceRange, sample_locs, DEPTH_RESUMMARIZE);